{"as_of":"2026-08-11T18:26:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:26ebf404d4f1de77325f3b6b5114ef3b4270d4663efba302c62fcad183dedc5f","coverage":[{"denominator":47,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":47,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-06T17:29:23.450957Z","state":"measured"},{"denominator":47,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":47,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-11T06:34:44.6726+00:00","state":"measured"},{"denominator":0,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"cited_works","source_observed_at":null,"state":"measured"}],"external_citation_measurements":[],"inbound":[],"links":{"evidence":"/evidence","html":"/paper/2507.10912/citation-record","integrity":"/paper/2507.10912/integrity","json":"/paper/2507.10912/citation-record.json","paper":"/paper/2507.10912"},"outbound":[{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:31.066734Z","title":"On area/depth trade-off in lut-based fpga technology mapping","venue":null,"work_id":"196c83eb-864c-4afb-8506-d595d0b199a9","year":1993},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:19.704398Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:5221448af4128c4f07c6c31bc827f872abe79d9be22c998d37ce68224c30fa65","observation_id":"1939a70d-f63b-4736-b26b-423614030306","resolution":{"observed_at":"2026-08-06T17:29:31.146725Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:30.892589Z","title":"Flowmap: An optimal technology mapping algorithm for delay optimization in lookup-table based fpga designs","venue":null,"work_id":"3f103fd0-8149-4424-ac91-bf0118638d1a","year":1994},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:19.763629Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:e51048fa9011db46c20d9d0cb368749095e4460efadbf090de25c39e9fd855c7","observation_id":"9e03c8b3-9cfd-4be2-8cf7-b19388b38073","resolution":{"observed_at":"2026-08-06T17:29:30.965684Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:30.743751Z","title":"Complexity of the lookup- table minimization problem for fpga technology mapping","venue":null,"work_id":"d57fea9a-58dc-488c-b64c-504f9c6d3892","year":1994},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:19.823391Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:b7d9d6a3d0f67068cc40839c2ce2b126a13ff35b978964351b3d6096c01c1a25","observation_id":"69bbc5a7-567f-4b35-a64c-e3d6cf499cd9","resolution":{"observed_at":"2026-08-06T17:29:30.801447Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:30.574071Z","title":"Low-power technology mapping for fpga architectures with dual supply voltages","venue":null,"work_id":"60949a20-7f85-4277-b46d-a47d47cbb313","year":2004},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:19.915514Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:39a9ecab0b6efba08c2d39b083dbd6a1d3734d0b4a1fdf5ad1408d045510354e","observation_id":"dd61b009-a761-4cbc-916c-739d784973d5","resolution":{"observed_at":"2026-08-06T17:29:30.652778Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:30.407146Z","title":"Improvements to technology mapping for lut-based fpgas","venue":null,"work_id":"86f78f77-51ba-4848-b6d2-84d35dfad8da","year":2006},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:20.018438Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:923a5ceb5e8fdeb53d253aeec665d5d2931843ab9f53c54c19efbb5bf0b8192a","observation_id":"913ee486-5363-4286-b23d-249695177031","resolution":{"observed_at":"2026-08-06T17:29:30.479999Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:30.285110Z","title":"Fpga technology mapping: a study of optimality","venue":null,"work_id":"b8a1ae77-a838-4727-a17e-43b31e848141","year":2005},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:20.111634Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:2fa4e5583b641a7cc66078a6fd25dcc84883decf63d8d86a304e9ef23043944c","observation_id":"e5245bf6-8d04-402b-ac97-8d0f2a86c419","resolution":{"observed_at":"2026-08-06T17:29:30.320956Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:30.097198Z","title":"Technology mapping for fpgas with embedded memory blocks","venue":null,"work_id":"75d27b33-a1f0-4fa2-a147-0787f0339bd8","year":1998},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:20.202314Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:2063538bef2940a7c12e9a4f739007d902e70c82c6d1da45b631ac311ceece50","observation_id":"3e524b64-5665-41a1-b495-0b8731f655ae","resolution":{"observed_at":"2026-08-06T17:29:30.201501Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:29.959861Z","title":"Combinational profiles of sequential benchmark circuits","venue":null,"work_id":"d0fed290-9f05-49fc-9e2a-0445e7735c0b","year":1989},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:20.264052Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:5de977ca974e3a521667e3d3bad20b5f91d547242f3c237fd9f9dfd755e11cd6","observation_id":"150c0207-4195-4be9-83f4-d30397d3dd36","resolution":{"observed_at":"2026-08-06T17:29:30.004288Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:29.794454Z","title":"VTR 8.0: Next generation architecture and CAD system for FPGAs","venue":null,"work_id":"a6a61adf-a97b-4fa4-a395-a497740ace81","year":2014},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:20.309785Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:f429e1c92acdf3e6953970f10ef4b74faa6710a506477102d3bc96cf46e94554","observation_id":"9dd812f1-0f19-489f-a34c-9c50a4720cc7","resolution":{"observed_at":"2026-08-06T17:29:29.881732Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"1805.05121","last_updated":"2022-06-03T09:33:52Z","snapshot_observed_at":"2026-08-06T23:04:31.677224Z","submitted_at":"2018-05-14T11:34:47Z","title":"The EPFL Logic Synthesis Libraries","version":3},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"1805.05121","snapshot_observed_at":"2026-08-06T17:29:20.390547Z","title":"The epfl logic synthesis libraries","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:20.390547Z"},"links":{"cited_paper":"/paper/1805.05121","citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:68ecfe7c48dc14e1bfc8c85228b802708eb804cc57cf6253fde5525fce5df174","observation_id":"1694d0d3-c9b1-49d4-be20-05eebe20e94d","resolution":{"observed_at":"2026-08-06T17:29:20.390547Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:29.525892Z","title":"Tree-based mapping of algorithms to predefined structures","venue":null,"work_id":"cdc83163-aada-40fd-8ea4-70df75905cb4","year":1993},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:20.499076Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:dd3c2aaa92752d17f5cb3acccee73c4119547557d90132147f8d0354bb8e5342","observation_id":"fe68fb81-cf1f-47dc-bfc3-5d34c305785f","resolution":{"observed_at":"2026-08-06T17:29:29.678784Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:29.302700Z","title":"Technology Mapping with Boolean Matching, Supergates and Choices","venue":null,"work_id":"7697663d-46da-49c3-bdd5-940d6489f755","year":2005},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:20.640750Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:41d2f5b7db5bec07c17d61ea36facee673680d93db1618b4089b1f85bc069445","observation_id":"5e8d32e9-2547-463e-bb49-3fc00aa41078","resolution":{"observed_at":"2026-08-06T17:29:29.406375Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:29.134884Z","title":null,"venue":null,"work_id":"b9b97190-62f9-4caa-b297-fb8ce3fdcd8f","year":2006},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:20.742422Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:7a1835ef1f137c173424b4f73422341b1100689b3c4548fefb32ff61f4583015","observation_id":"e8884f14-65f4-4ffd-ab60-8e4d404dee4a","resolution":{"observed_at":"2026-08-06T17:29:29.206712Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:28.849241Z","title":"Read your circuit: leveraging word embedding to guide logic optimization","venue":null,"work_id":"1b084d7c-05c3-4da4-b49e-fbcda96a6160","year":2021},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:20.849757Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:4db1bcede494f4f4e7a1469f15b77c6cbd316c7d440bf37cc230c572ebab098c","observation_id":"2665931f-2cc1-4a6a-a94a-8a6344c34ce5","resolution":{"observed_at":"2026-08-06T17:29:28.996338Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:28.518907Z","title":"Boolgebra: Attributed graph-learning for boolean algebraic manipulation","venue":null,"work_id":"d4e6fec1-f04a-43e9-ae14-2c39d1840b7b","year":2024},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:20.948637Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:a63576490a53e34fd86e2b0c88f7f10273280b271733054d858fe37d5d7652f5","observation_id":"e6748fdb-6f1b-4146-ac54-0b59ca3fb0e9","resolution":{"observed_at":"2026-08-06T17:29:28.672547Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:28.208919Z","title":"Slap: A supervised learning approach for priority cuts technology mapping","venue":null,"work_id":"e103693d-4773-404f-90fb-0920c301b32c","year":2021},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:21.040237Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:5b142ae08a95e42d5530c04058f8647f46e270a5a2286ee7f1f93784b1292212","observation_id":"dcc950c0-e994-4ddf-bca0-f2d8e454029a","resolution":{"observed_at":"2026-08-06T17:29:28.325656Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:27.908539Z","title":"Nvcell: Standard cell layout in advanced technology nodes with reinforcement learning","venue":null,"work_id":"291c4c5d-64f8-40d5-b8b3-226146cd3af2","year":2021},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:21.106661Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:b7532452dba9ffe652eb5d52e9bd649bfdc8242dc7f98fb2be8c8dea80107da4","observation_id":"932fd7bf-bec6-4388-824c-822274121bbd","resolution":{"observed_at":"2026-08-06T17:29:28.039390Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:27.716376Z","title":"InTime: A Machine Learning Approach for Efficient Selection of FPGA CAD Tool Parameters","venue":null,"work_id":"65d50503-7ad2-4246-b95e-724e90614e69","year":2015},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:21.186464Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:704552c72e66af7bceef8e6f2938adac31b436da37a2fe61d8921f4ef9c78536","observation_id":"41e9bd08-18d6-4959-be96-f2538cbecc9f","resolution":{"observed_at":"2026-08-06T17:29:27.791191Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:27.500902Z","title":"LAMDA: Learning-Assisted Multi-stage Autotuning for FPGA Design Closure","venue":null,"work_id":"192e3d71-900d-4c8b-bec9-b9f092d5d11d","year":null},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:21.244629Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:678d5ed2727d46d043039ed2253ef12833493c7449e84dc95cc29901d358037e","observation_id":"bcc9dcea-a6e8-4300-b2fd-bd82dbf5304b","resolution":{"observed_at":"2026-08-06T17:29:27.601743Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:27.133997Z","title":"Ziegler, Ramon Bertran Monfort, Alper Buyuktosunoglu, and Pradip Bose","venue":null,"work_id":"455c84bf-72c0-47eb-8d81-228d4a628af9","year":2017},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:21.320082Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:2106b3036e6c58e54a835ec1d4c2ff4ddd0d31f74a008ea015b57b0ca1dd2e2f","observation_id":"234c5fec-d71e-478d-af4f-32516a4e41eb","resolution":{"observed_at":"2026-08-06T17:29:27.345245Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:26.914542Z","title":"Developing synthesis flows without human knowledge","venue":null,"work_id":"8a936961-6ec5-47a3-8726-b2135b76106d","year":2018},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":21,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:21.432858Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:4e454e8a494454c425e23f53bb5272c21a352cc470c905960c43e0c775e27b80","observation_id":"f5c86be2-555a-4532-9db5-42659fb910d4","resolution":{"observed_at":"2026-08-06T17:29:27.047159Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"1911.04021","last_updated":"2019-11-13T04:07:24Z","snapshot_observed_at":"2026-07-06T08:35:57.238916Z","submitted_at":"2019-11-11T00:38:39Z","title":"DRiLLS: Deep Reinforcement Learning for Logic Synthesis","version":2},"cited_work":{"arxiv_id":"1911.04021","doi":null,"metadata_source":"pith","pith_arxiv_id":"1911.04021","snapshot_observed_at":"2026-08-06T17:29:23.568258Z","title":"DRiLLS: Deep Reinforcement Learning for Logic Synthesis","venue":"cs.AI","work_id":"2b67f835-3516-406e-a960-da05c735a24b","year":2019},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:21.496709Z"},"links":{"cited_paper":"/paper/1911.04021","citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:748a26287e25771fe2427a1244e8579d3256e17246f32b629c27baa1235a5e40","observation_id":"7f409294-fa99-4545-b0eb-bfe91717e36d","resolution":{"observed_at":"2026-08-06T17:29:23.608137Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:26.755843Z","title":"High performance graph convolutional networks with applications in testability analysis","venue":null,"work_id":"0003d8a6-b485-48ba-9e5a-7fc8b7ac38a6","year":2019},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":23,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:21.541368Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:2f806a35c334830c5bd7d8cc0f26a0d5c41256fc30c762dfbe054a0151b2da51","observation_id":"e1563105-750a-4c3e-bb50-5f259ca8768c","resolution":{"observed_at":"2026-08-06T17:29:26.852533Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:26.560960Z","title":"Decision making in synthesis cross technologies using lstms and transfer learning","venue":null,"work_id":"89f1631f-2b03-4236-a4f4-024c86f84418","year":2020},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":24,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:21.606065Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:68542f959e02679c2c3d356d2d2e19dd0dbf188836587f53f935cd9655963e64","observation_id":"71e8e469-9c3a-42ec-91f1-499e13bf0a67","resolution":{"observed_at":"2026-08-06T17:29:26.667138Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:26.444364Z","title":"Flowtune: Practical multi-armed bandits in boolean optimiza- tion","venue":null,"work_id":"207eead1-68f4-47e8-a199-2df8ca336ae9","year":2020},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":25,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:21.683026Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:e5483d78329156d54d681543895bf746e5e73e547315e838b6922b7d1c4dd3eb","observation_id":"30c89e53-b179-49a6-be36-574da6804522","resolution":{"observed_at":"2026-08-06T17:29:26.497088Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:26.290699Z","title":"Flowtune: End-to-end automatic logic optimization exploration via domain-specific multi-armed bandit","venue":null,"work_id":"29327a02-c1bf-4fc9-b525-22de72c0d367","year":2022},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":26,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:21.779878Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:b6c89ffffdb285d3297864f23b5a714a48a85f1b5275a723329336ee5fba484a","observation_id":"b6226b70-40c4-45fb-bb85-0fd7004acd1d","resolution":{"observed_at":"2026-08-06T17:29:26.363226Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:26.147120Z","title":"Machine learning for agile fpga design","venue":null,"work_id":"9845ca21-957a-4036-87ea-3dbcb144c101","year":2022},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":27,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:21.838176Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:3a9a958cb646088e7b515d0f1e77f9a31785a25dad9dee905cdf7957564323b6","observation_id":"716116d7-29d6-4e87-92f1-8e876206f430","resolution":{"observed_at":"2026-08-06T17:29:26.230717Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:26.020566Z","title":"Efficient Design Space Exploration via Statistical Sampling and AdaBoost Learning","venue":null,"work_id":"df0e00c4-2c07-4ad4-9681-7099012b5100","year":2016},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":28,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:21.939074Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:41f422e0b24be09ae67c441b04e529c6fee26b355314a4dffaeb9cb867d364b2","observation_id":"0eb4d4ad-afa0-4312-9c3e-ff3ffeddf702","resolution":{"observed_at":"2026-08-06T17:29:26.080780Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:25.876822Z","title":"Maptune: Advancing asic technology mapping via reinforcement learning guided library tuning","venue":null,"work_id":"5e635f0e-5402-4339-b08f-91e1943b38ee","year":2024},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":29,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:22.044543Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:fa2cd3540fe6d2660bfefcc97670c1ed1f79dffb6d8bce44dd51fb433679cac0","observation_id":"8a14c865-7da3-4b85-a728-106714ff7039","resolution":{"observed_at":"2026-08-06T17:29:25.907700Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:25.749866Z","title":"Verilog-to- pyg-a framework for graph learning and augmentation on rtl designs","venue":null,"work_id":"bf4b7a0d-d1c6-4966-a186-bee981da97f5","year":2023},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":30,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:22.146393Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:ddad56ae6bc9d7bf1e3b7c839c606e261f204d8800d19b1b57a5e559aee96bde","observation_id":"c1b2e3af-3bb9-4b59-98cf-731cb0915847","resolution":{"observed_at":"2026-08-06T17:29:25.793922Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:25.594630Z","title":"E-syn: E-graph rewriting with technology-aware cost functions for logic synthesis","venue":null,"work_id":"1e80c8af-dedc-4a3c-a290-de6daacce170","year":2024},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":31,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:22.215781Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:ad5c74732d9fdf31700912e406442e9a736d44d1a58eaeb29bc1d7fcda0035f4","observation_id":"dd6fa068-f0eb-44ad-8cb5-787bc2e07e7c","resolution":{"observed_at":"2026-08-06T17:29:25.695887Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:25.477776Z","title":"Gamora: Graph learning based symbolic reasoning for large-scale boolean networks","venue":null,"work_id":"a47a0609-a327-4eb5-8455-118667dde2d5","year":2023},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":32,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:22.302109Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:a71a0612a1754a720fb16a4e01d80eb21a34eae94c7e4c9b07e109ccdd23eca0","observation_id":"1adac7fc-d5a4-401c-abdd-5b30f40509f1","resolution":{"observed_at":"2026-08-06T17:29:25.529052Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:25.307174Z","title":"Less is more: Hop-wise graph attention for scalable and generalizable learning on circuits","venue":null,"work_id":"4dd9dfcc-b8cc-4952-aa8a-ab65023b9a39","year":2024},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":33,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:22.407067Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:c86119d767448c19e23b9b129b6e1af85cd49c8218cb812cc9bf2f7197606a89","observation_id":"aaff7ec2-1772-4291-9999-576f2267ea77","resolution":{"observed_at":"2026-08-06T17:29:25.391900Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:25.177307Z","title":"Smoothe: Differentiable e-graph extraction","venue":null,"work_id":"a884fbe4-ac50-4175-a653-550bdfbeae3e","year":2025},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":34,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:22.464285Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:e28079867a7b3033edfcb8d370f9b985ad9e9edb67443e074ab21fe5b135a8fd","observation_id":"2b6f9199-4a86-4023-b08e-8e390d9fdc31","resolution":{"observed_at":"2026-08-06T17:29:25.227036Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:25.053352Z","title":"Differ- entiable combinatorial scheduling at scale","venue":null,"work_id":"9b8b48ed-6309-4e48-a283-305d0994a966","year":2024},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":35,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:22.541431Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:52681cd82f8549db9b69303307e94363e0846a8af8b4fb686ad87fadb77e6af5","observation_id":"fd6bc52f-d686-448d-8117-d3b5eb6e3a75","resolution":{"observed_at":"2026-08-06T17:29:25.102872Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:24.930446Z","title":"Respect: Reinforcement learning based edge scheduling on pipelined coral edge tpus","venue":null,"work_id":"ab8ef91d-6216-4b41-ac7c-6a37dd0b9267","year":2023},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":36,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:22.666723Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:baeb5bc2f128fd779fa903898c50d71ec047ad537ed0054458c1c7d5546251fe","observation_id":"11e90544-651c-4ae4-ada4-a56d929c5e51","resolution":{"observed_at":"2026-08-06T17:29:24.981940Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:24.778026Z","title":"Accelerating exact combinatorial optimization via rl-based initialization-a case study in scheduling","venue":null,"work_id":"c8ade237-f6e5-4772-b261-bf1d7645ad91","year":2023},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":37,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:22.779824Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:2e62039e15ee59aa1c7a1e220412b95fdc03c88d5d130170546fc6d81485a8a0","observation_id":"8ff4ae6e-b525-4da9-9fd4-84ac38915ce3","resolution":{"observed_at":"2026-08-06T17:29:24.828343Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:24.682982Z","title":"Cbtune: Contextual bandit tuning for logic synthesis","venue":null,"work_id":"c89e7a60-591e-45f3-8009-5d51f51086cc","year":2024},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":38,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:22.852342Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:d3a8d1073928a37514ca3943bdca82029ca94181173d6a7b406c7c51036cb035","observation_id":"fd1e889d-1eff-4cb7-bcd1-b3d9995b9074","resolution":{"observed_at":"2026-08-06T17:29:24.716604Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:24.580316Z","title":"Abc: A system for sequential synthesis and verification","venue":null,"work_id":"2e926295-aad0-40d7-8d0a-41b15e9ca60a","year":2007},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":39,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:22.907628Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:01d7939fe0ebdfe29dd11c7955d5d47a35a8cc24bdb2fb777dfa9bf0ec0dec0a","observation_id":"4ec30de5-fef9-4db7-9303-323f862caa95","resolution":{"observed_at":"2026-08-06T17:29:24.608037Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:24.443225Z","title":"ABC: An Academic Industrial- strength Verification tool","venue":null,"work_id":"a3923ba2-eee3-4934-a819-7ac2dd3076be","year":2010},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":40,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:22.980204Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:18eb1eaa73c1ff6c73b7d901e065610dbce4badbf6ac5b74d3da35c560cbc8a8","observation_id":"8c48e92f-c28c-4108-8478-da3a1a33bf38","resolution":{"observed_at":"2026-08-06T17:29:24.495065Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:24.304500Z","title":"Painting on placement: Forecasting routing congestion using conditional generative adversarial nets","venue":null,"work_id":"f0ece343-8e54-46fb-8147-dae72f641441","year":2019},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":41,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:23.052189Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:ab24b0ed6df4a00054d60abfd91f7b0cb668b4ccb35ccd0ee15ad28a5b165e83","observation_id":"61a15b9f-e8fa-4c0a-8502-05b314ae11b9","resolution":{"observed_at":"2026-08-06T17:29:24.380471Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:24.195934Z","title":"Fast and accurate estimation of quality of results in high-level synthesis with machine learning","venue":null,"work_id":"82fb538d-eb00-49a8-a9f5-7a2245aac75f","year":2018},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":42,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:23.132553Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:d80518fd950859029c1613adf1db690865c377b74837f28a5aff215b46d32019","observation_id":"c38d456d-62ee-43ba-9970-295102790bd8","resolution":{"observed_at":"2026-08-06T17:29:24.231371Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:24.085384Z","title":"Robust gnn-based representation learning for hls","venue":null,"work_id":"382ba747-1811-4f57-a1e5-2439ca492167","year":2023},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":43,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:23.175199Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:865a8366a5875ff8723745f153183ff62ef93a3bb02ca18d3674f5fc74a21a14","observation_id":"9c7d078b-ed45-43ef-a6ec-16b11c3b3e5f","resolution":{"observed_at":"2026-08-06T17:29:24.131777Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"1402.6028","last_updated":"2014-02-25T01:34:43Z","snapshot_observed_at":"2026-07-06T03:36:51.545768Z","submitted_at":"2014-02-25T01:34:43Z","title":"Algorithms for multi-armed bandit problems","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"1402.6028","snapshot_observed_at":"2026-08-06T17:29:23.269942Z","title":"Algorithms for multi-armed bandit problems","venue":null,"work_id":null,"year":2014},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":44,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:23.269942Z"},"links":{"cited_paper":"/paper/1402.6028","citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:cc70a1039a7d7be509bdfcc52ec791fecfcbe9bf434deec2ec26ae4fcd5d908b","observation_id":"dcc364e4-b522-4ef3-8f6c-441f48b432c8","resolution":{"observed_at":"2026-08-06T17:29:23.269942Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:23.959555Z","title":"Upper confidence bound based decision making strategies and dynamic spectrum access","venue":null,"work_id":"62302f8b-73d0-4822-aca6-6a57fdd2b321","year":2010},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":45,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:23.350206Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:11224ba87f9349ab1e23168adb7c96231d11598faf88e43cdad90b8ca8539bde","observation_id":"77547202-1c0c-4407-806c-f9d133beab6d","resolution":{"observed_at":"2026-08-06T17:29:24.015090Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:23.823369Z","title":"Asap7: A 7-nm finfet predictive process design kit","venue":null,"work_id":"8da0a72f-c91f-430f-8ad9-10a52dfed73e","year":2016},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":46,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:23.405758Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:72e8b487da6997549fd91d6996de32eebf9126d1fef81159f2aa9a90ae7f86e9","observation_id":"0dad2c26-bcae-471e-990e-6a9dec83ee2b","resolution":{"observed_at":"2026-08-06T17:29:23.894135Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T17:29:23.704186Z","title":"URL https://eda.ncsu.edu/freepdk/freepdk45/","venue":null,"work_id":"0bf241f8-9505-4196-bc36-6b9e90bc3022","year":null},"citing_paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper","version":1},"reference_index":47,"source":"pdf_text","source_observed_at":"2026-08-06T17:29:23.450957Z"},"links":{"citing_paper":"/paper/2507.10912"},"observation_digest":"sha256:ec543c09d10daa467ef3b4f649622dd4e32dcf09ca0346da4c69aca98edd08b2","observation_id":"c028f314-000e-49be-9906-828ee7f55928","resolution":{"observed_at":"2026-08-06T17:29:23.766123Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-11T06:34:44.6726+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"state":"measured"}}],"paper":{"arxiv_id":"2507.10912","last_updated":"2025-07-15T02:08:36Z","latest_version":1,"primary_category":"cs.AR","snapshot_observed_at":"2026-08-09T05:02:10.993186Z","submitted_at":"2025-07-15T02:08:36Z","title":"Mapping Fusion: Improving FPGA Technology Mapping with ASIC Mapper"},"reference_resolution":{"displayed":47,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":3,"verified_exact":1,"verified_fuzzy":43},"total_outbound_references":47},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-11T06:34:44.6726+00:00","source":"crossref"},{"observed_at":"2026-08-11T06:34:36.301508+00:00","source":"retraction_watch"}],"thesis":"As of 11 August 2026, this Paper Citation Record lists 47 of 47 outbound references and 0 inbound Pith citation observations for arXiv:2507.10912."}