{"as_of":"2026-08-07T10:34:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:ae65465f3bd2a239b4edf8bc560d7489b64cd2806c9ee7b42462c94adf81c286","coverage":[{"denominator":47,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":47,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-06T15:19:55.293263Z","state":"measured"},{"denominator":53,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":53,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-07T06:34:17.273281+00:00","state":"measured"},{"denominator":6,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":6,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-02T07:12:17.009828Z","state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"arxiv_reference","source_observed_at":"2026-05-21T06:54:01.159000Z","state":"measured"}],"external_citation_measurements":[],"inbound":[{"citation":{"cited_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"cited_work":{"arxiv_id":"2507.16200","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"2507.16200","snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","venue":null,"work_id":"242ffbb7-9aad-4947-a00a-9ea07f2d6eaf","year":2025},"citing_paper":{"arxiv_id":"2604.03144","last_updated":"2026-04-03T16:06:25Z","snapshot_observed_at":"2026-07-06T22:52:25.307426Z","submitted_at":"2026-04-03T16:06:25Z","title":"InCoder-32B-Thinking: Industrial Code World Model for Thinking","version":1},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-05-13T18:56:31.975626Z"},"links":{"cited_paper":"/paper/2507.16200","citing_paper":"/paper/2604.03144"},"observation_digest":"sha256:c7ddb384637ec3a0044990268273b0d2466ea551a494e34cdccc792e2161a93b","observation_id":"3d060298-2863-4600-a6f4-54045634113f","resolution":{"observed_at":"2026-05-13T18:58:08.723913Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"cited_work":{"arxiv_id":"2507.16200","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"2507.16200","snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","venue":null,"work_id":"242ffbb7-9aad-4947-a00a-9ea07f2d6eaf","year":2025},"citing_paper":{"arxiv_id":"2604.08932","last_updated":"2026-04-10T04:00:49Z","snapshot_observed_at":"2026-07-06T22:57:55.179136Z","submitted_at":"2026-04-10T04:00:49Z","title":"From Indiscriminate to Targeted: Efficient RTL Verification via Functionally Key Signal-Driven LLM Assertion Generation","version":1},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-05-10T17:26:47.139265Z"},"links":{"cited_paper":"/paper/2507.16200","citing_paper":"/paper/2604.08932"},"observation_digest":"sha256:2365bbfcf6dae30e4055f50fb73d3c1a28561dc00f36b2372980ca0bc4884920","observation_id":"5854c317-683e-48a4-ba1b-fe007e1d0b52","resolution":{"observed_at":"2026-05-11T06:46:50.008880Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"cited_work":{"arxiv_id":"2507.16200","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"2507.16200","snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","venue":null,"work_id":"242ffbb7-9aad-4947-a00a-9ea07f2d6eaf","year":2025},"citing_paper":{"arxiv_id":"2604.27643","last_updated":"2026-04-30T09:35:32Z","snapshot_observed_at":"2026-07-06T23:13:07.378140Z","submitted_at":"2026-04-30T09:35:32Z","title":"HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs","version":1},"reference_index":35,"source":"pdf_text","source_observed_at":"2026-05-07T05:32:07.097013Z"},"links":{"cited_paper":"/paper/2507.16200","citing_paper":"/paper/2604.27643"},"observation_digest":"sha256:5cd6b8566de921808ddc40507bc87518ff71be5e5f344246d069a461dfc8ccbc","observation_id":"facd681e-8744-40e9-af29-076ab749e297","resolution":{"observed_at":"2026-05-12T10:36:29.758607Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"cited_work":{"arxiv_id":"2507.16200","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"2507.16200","snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","venue":null,"work_id":"242ffbb7-9aad-4947-a00a-9ea07f2d6eaf","year":2025},"citing_paper":{"arxiv_id":"2605.20456","last_updated":"2026-05-19T20:10:13Z","snapshot_observed_at":"2026-08-03T00:27:17.336240Z","submitted_at":"2026-05-19T20:10:13Z","title":"Agentic Agile-V: From Vibe Coding to Verified Engineering in Software and Hardware Development","version":1},"reference_index":30,"source":"pdf_text","source_observed_at":"2026-05-21T06:51:24.566343Z"},"links":{"cited_paper":"/paper/2507.16200","citing_paper":"/paper/2605.20456"},"observation_digest":"sha256:b9e47aa0b835ae8de9b81bff3d074409911c9e643b2d52c2c5b4c5a2e6221b54","observation_id":"0e0e407f-a3e4-4ec5-8518-7015254148b5","resolution":{"observed_at":"2026-05-21T06:54:01.160526Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2507.16200","snapshot_observed_at":"2026-08-02T07:12:17.009828Z","title":null,"venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2607.13079","last_updated":"2026-07-20T02:21:21Z","snapshot_observed_at":"2026-08-07T01:24:26.906140Z","submitted_at":"2026-07-12T23:38:38Z","title":"ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation","version":2},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-02T07:12:17.009828Z"},"links":{"cited_paper":"/paper/2507.16200","citing_paper":"/paper/2607.13079"},"observation_digest":"sha256:339cf99a2d76656e74fbd0f83184844090a619230b09b9c78de7b7941549ea8c","observation_id":"7597c667-dc5c-47ac-8d42-2d3e5f4c3269","resolution":{"observed_at":"2026-08-02T07:12:17.009828Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2507.16200","snapshot_observed_at":"2026-08-01T17:46:03.778892Z","title":null,"venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2607.17528","last_updated":"2026-07-23T03:04:35Z","snapshot_observed_at":"2026-08-06T05:13:26.667452Z","submitted_at":"2026-07-20T04:08:06Z","title":"Can AI Agents Really Complete RTL-to-GDS? Lessons from Benchmarking Tool-Interactive EDA Workflows","version":3},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-01T17:46:03.778892Z"},"links":{"cited_paper":"/paper/2507.16200","citing_paper":"/paper/2607.17528"},"observation_digest":"sha256:7b0430fffaad5f4ae645905e71c7bac4cbf2168f07d8e85e951dbab67cb67012","observation_id":"a2a04a83-78e9-4ae1-b346-d4bd5c8021d8","resolution":{"observed_at":"2026-08-01T17:46:03.778892Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}}],"links":{"evidence":"/evidence","html":"/paper/2507.16200/citation-record","integrity":"/paper/2507.16200/integrity","json":"/paper/2507.16200/citation-record.json","paper":"/paper/2507.16200"},"outbound":[{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T15:19:57.678668Z","title":"For better or worse, benchmarks shape a field,","venue":null,"work_id":"b5283a70-558d-4ed4-bb0c-0a3d71c92479","year":2012},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:52.018481Z"},"links":{"citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:73196a7786a413c9a32a10086755fe825a501e7be895d03db2f42eca776a40e3","observation_id":"217b35be-7ec9-4165-9379-2bc8e60f44af","resolution":{"observed_at":"2026-08-06T15:19:57.682062Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2303.08774","last_updated":"2024-03-04T06:01:33Z","snapshot_observed_at":"2026-08-07T07:30:12.213965Z","submitted_at":"2023-03-15T17:15:04Z","title":"GPT-4 Technical Report","version":6},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2303.08774","snapshot_observed_at":"2026-08-06T15:19:52.089595Z","title":"Gpt-4 technical report,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:52.089595Z"},"links":{"cited_paper":"/paper/2303.08774","citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:e1a553f39ec2ac6aa7ca3cbbc131e6f7b21ab9286c07a213abbf6c05d5c9d671","observation_id":"ed612326-f117-484a-ba1b-881e910aefac","resolution":{"observed_at":"2026-08-06T15:19:52.089595Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.00176","last_updated":"2024-04-04T20:18:57Z","snapshot_observed_at":"2026-07-06T16:41:27.099792Z","submitted_at":"2023-10-31T22:35:58Z","title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.00176","snapshot_observed_at":"2026-08-06T15:19:52.190982Z","title":"Chipnemo: Domain- adapted llms for chip design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:52.190982Z"},"links":{"cited_paper":"/paper/2311.00176","citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:54cbb637d9c02d88a66cf76755da221b1892879af82596329a08b73833774c39","observation_id":"f498e9d2-442d-4d49-b3b7-b86199dfd14f","resolution":{"observed_at":"2026-08-06T15:19:52.190982Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2312.08617","last_updated":"2025-08-06T13:02:31Z","snapshot_observed_at":"2026-07-06T17:01:26.660741Z","submitted_at":"2023-12-14T02:42:15Z","title":"RTLCoder: Outperforming GPT-3.5 in Design RTL Generation with Our Open-Source Dataset and Lightweight Solution","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2312.08617","snapshot_observed_at":"2026-08-06T15:19:52.253221Z","title":"Rtlcoder: Outper- forming gpt-3.5 in design rtl generation with our open-source dataset and lightweight solution,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:52.253221Z"},"links":{"cited_paper":"/paper/2312.08617","citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:c7fff4cea40b47d4d10036ed06b1057117b3c44454f230984a3012fe6525f08e","observation_id":"84c0b0b9-c2a6-4899-9341-9ccb86a0d787","resolution":{"observed_at":"2026-08-06T15:19:52.253221Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2402.03375","last_updated":"2024-05-02T09:18:21Z","snapshot_observed_at":"2026-07-31T17:32:40.291560Z","submitted_at":"2024-02-03T08:00:12Z","title":"BetterV: Controlled Verilog Generation with Discriminative Guidance","version":3},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2402.03375","snapshot_observed_at":"2026-08-06T15:19:52.329639Z","title":"Betterv: Con- trolled verilog generation with discriminative guidance,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:52.329639Z"},"links":{"cited_paper":"/paper/2402.03375","citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:0a8b2bf06a02769a746bce7f958220a053d1ed10d399175985c21e122d02052a","observation_id":"8b535f76-efe3-42bc-9363-9b88b2a1966e","resolution":{"observed_at":"2026-08-06T15:19:52.329639Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2407.01910","last_updated":"2024-07-03T15:15:20Z","snapshot_observed_at":"2026-07-06T18:40:01.321429Z","submitted_at":"2024-07-02T03:21:24Z","title":"MG-Verilog: Multi-grained Dataset Towards Enhanced LLM-assisted Verilog Generation","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2407.01910","snapshot_observed_at":"2026-08-06T15:19:52.391272Z","title":"Mg-verilog: Multi-grained dataset towards enhanced llm-assisted verilog generation,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:52.391272Z"},"links":{"cited_paper":"/paper/2407.01910","citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:d8a7a2a396fbf5b46c4e779e0877e5de653fd68129e17466fc215b2a77eec1c9","observation_id":"2bfb09c1-36c3-425a-80c4-61964f959cc9","resolution":{"observed_at":"2026-08-06T15:19:52.391272Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2407.10424","last_updated":"2025-05-11T07:35:24Z","snapshot_observed_at":"2026-07-06T18:46:14.144689Z","submitted_at":"2024-07-15T03:57:20Z","title":"CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarization","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2407.10424","snapshot_observed_at":"2026-08-06T15:19:52.497138Z","title":"Codev: Empowering llms for verilog generation through multi-level summarization,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:52.497138Z"},"links":{"cited_paper":"/paper/2407.10424","citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:9be8d72ee8609a8b50afed5cade75de41edc1f0933d08a3b2430fe6fcf578e96","observation_id":"892fc982-7977-4821-90dc-29c55e5fc431","resolution":{"observed_at":"2026-08-06T15:19:52.497138Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2403.11202","last_updated":"2024-07-10T09:06:40Z","snapshot_observed_at":"2026-08-07T05:04:38.637893Z","submitted_at":"2024-03-17T13:01:03Z","title":"Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework","version":2},"cited_work":{"arxiv_id":"2403.11202","doi":null,"metadata_source":"pith","pith_arxiv_id":"2403.11202","snapshot_observed_at":"2026-08-06T15:19:55.807021Z","title":"Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework","venue":"cs.AR","work_id":"6ad4d54f-020e-4fd7-ac78-30861aef3370","year":2024},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:52.549242Z"},"links":{"cited_paper":"/paper/2403.11202","citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:99779bd2ca1726e3f8c9cd90e8eecd0c19f165e6a61dbc73692ca3e98b4715d1","observation_id":"10c52c32-caab-4bfe-a8f0-524dfcfd82ca","resolution":{"observed_at":"2026-08-06T15:19:55.859908Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2407.18333","last_updated":"2024-07-21T16:42:45Z","snapshot_observed_at":"2026-07-06T18:52:07.765911Z","submitted_at":"2024-07-21T16:42:45Z","title":"AutoVCoder: A Systematic Framework for Automated Verilog Code Generation using LLMs","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2407.18333","snapshot_observed_at":"2026-08-06T15:19:52.617478Z","title":"Autovcoder: A systematic framework for automated verilog code generation using llms,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:52.617478Z"},"links":{"cited_paper":"/paper/2407.18333","citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:be0c1b96cbd6baad35cd086ec9c79c2edc170abf0028a4a5259afc9c7c10051e","observation_id":"536449ab-59c9-49f3-bb65-ba1989259657","resolution":{"observed_at":"2026-08-06T15:19:52.617478Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2409.12993","last_updated":"2025-02-06T21:39:27Z","snapshot_observed_at":"2026-08-06T09:50:18.968063Z","submitted_at":"2024-09-19T12:15:55Z","title":"CraftRTL: High-quality Synthetic Data Generation for Verilog Code Models with Correct-by-Construction Non-Textual Representations and Targeted Code Repair","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2409.12993","snapshot_observed_at":"2026-08-06T15:19:52.696047Z","title":"Craftrtl: High-quality synthetic data generation for verilog code models with correct-by- construction non-textual representations and targeted code repair,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:52.696047Z"},"links":{"cited_paper":"/paper/2409.12993","citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:5362756dd40cd56d4aba399c94a79c1ab1debfbc6b0d2caa800eeb5442f520ea","observation_id":"fbc4af32-f4e2-4353-91f4-2aab8d6f620a","resolution":{"observed_at":"2026-08-06T15:19:52.696047Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2409.11411","last_updated":"2024-09-03T15:07:11Z","snapshot_observed_at":"2026-08-07T07:58:19.036088Z","submitted_at":"2024-09-03T15:07:11Z","title":"AIvril: AI-Driven RTL Generation With Verification In-The-Loop","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2409.11411","snapshot_observed_at":"2026-08-06T15:19:52.803326Z","title":"Aivril: Ai-driven rtl gen- eration with verification in-the-loop,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:52.803326Z"},"links":{"cited_paper":"/paper/2409.11411","citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:6a17195531cf1fc89172f3b8992b905fa6610592676b2eb4f951bc2e926e7cad","observation_id":"5ec9cfe7-e44a-4c7b-960d-e82e807e978a","resolution":{"observed_at":"2026-08-06T15:19:52.803326Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T15:19:57.666880Z","title":"Chipgpt: How far are we from natural language hardware design,","venue":null,"work_id":"2182e268-285e-4465-b603-d970430ea39e","year":2023},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:52.872152Z"},"links":{"citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:7922eb84ffeea440637a124e108df76e6a73ba5ba66e3ddac2abfd47a83705cd","observation_id":"54c08f54-0618-4645-9b44-5f5316ac8170","resolution":{"observed_at":"2026-08-06T15:19:57.671200Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T15:19:57.654337Z","title":"Chip-chat: Chal- lenges and opportunities in conversational hardware design,","venue":null,"work_id":"ded363e7-1a1a-496e-857e-b5d97dad1cd1","year":2023},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:52.963586Z"},"links":{"citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:938461b29125694f0e2ae9ee183893b0b9677b0b94a3fc17a18c57ec9e153af6","observation_id":"0917de2a-99c8-4b73-b86a-1594f0931044","resolution":{"observed_at":"2026-08-06T15:19:57.658153Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2409.11414","last_updated":"2024-09-04T09:59:37Z","snapshot_observed_at":"2026-08-03T17:47:44.483939Z","submitted_at":"2024-09-04T09:59:37Z","title":"RTLRewriter: Methodologies for Large Models aided RTL Code Optimization","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2409.11414","snapshot_observed_at":"2026-08-06T15:19:53.025192Z","title":"Rtlrewriter: Methodologies for large models aided rtl code optimization,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:53.025192Z"},"links":{"cited_paper":"/paper/2409.11414","citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:bd90c47e7279c05318e1987493a745b7c7ef0f42cb0c6597828c35344c94a4af","observation_id":"ad6362d0-0e6e-438e-baef-b3c23f524025","resolution":{"observed_at":"2026-08-06T15:19:53.025192Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2403.07257","last_updated":"2024-05-01T10:43:36Z","snapshot_observed_at":"2026-08-07T05:54:06.933164Z","submitted_at":"2024-03-12T02:26:30Z","title":"The Dawn of AI-Native EDA: Opportunities and Challenges of Large Circuit Models","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2403.07257","snapshot_observed_at":"2026-08-06T15:19:53.116262Z","title":"The dawn of ai-native eda: Promises and challenges of large circuit models,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:53.116262Z"},"links":{"cited_paper":"/paper/2403.07257","citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:fc738f96ad362eb3178b796ba96be926922c7f874fb959146f826f41b9936f80","observation_id":"b6a75014-a137-4de7-943b-a74f75678c88","resolution":{"observed_at":"2026-08-06T15:19:53.116262Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T15:19:53.161183Z","title":"Assertllm: Generating and evaluating hardware verification assertions from design specifications via multi-llms,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:53.161183Z"},"links":{"citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:b7b3781d25fdcedd640a1b55b4b038339b18cf9e70e5fdbb647168dec7854792","observation_id":"f5f15599-5dfd-4a14-b191-493a1f51d95d","resolution":{"observed_at":"2026-08-06T15:19:53.161183Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T15:19:57.642213Z","title":"Gpt4aigchip: Towards next-generation ai accelerator design automation via large language models,","venue":null,"work_id":"823d7fce-2bc2-40ec-b7c3-67b735122549","year":2023},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:53.224221Z"},"links":{"citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:fe0425fd3f361b44451d6e38f1310b88f88f01a4d18a4053adeb6aded1741eb7","observation_id":"0cc11326-5618-48db-82dc-f52468efd028","resolution":{"observed_at":"2026-08-06T15:19:57.646026Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T15:19:57.632505Z","title":"Chateda: A large language model powered autonomous agent for eda,","venue":null,"work_id":"816cc468-fec8-4ec0-8031-2bd53a41d8d1","year":2024},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:53.286159Z"},"links":{"citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:eac522085ecb1cd86482051652dd3512204f8d661e680db612f0cc2326163192","observation_id":"d4114799-3e06-49f9-8a5e-8a2a1aaf4597","resolution":{"observed_at":"2026-08-06T15:19:57.635822Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2306.14027","last_updated":"2024-07-09T21:08:06Z","snapshot_observed_at":"2026-08-01T16:10:21.917476Z","submitted_at":"2023-06-24T17:44:36Z","title":"(Security) Assertions by Large Language Models","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2306.14027","snapshot_observed_at":"2026-08-06T15:19:53.331516Z","title":"Llm-assisted generation of hardware assertions,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:53.331516Z"},"links":{"cited_paper":"/paper/2306.14027","citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:1c5c1b85881b9880dd7d17466635b068e829fe64ce0ac92ec59a089212773dbc","observation_id":"0b26ba63-56e8-4b94-95e7-886d6f1cb97a","resolution":{"observed_at":"2026-08-06T15:19:53.331516Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T15:19:53.422372Z","title":"Rtlfixer: Automatically fixing rtl syntax errors with large language model,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:53.422372Z"},"links":{"citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:a037843986226bdc74066545bd892ac4a19acb48680d2101c232bfe40dc8bf52","observation_id":"b346fadf-9b17-4209-b2ca-a16f4d358f63","resolution":{"observed_at":"2026-08-06T15:19:53.422372Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2403.11671","last_updated":"2024-03-18T11:19:37Z","snapshot_observed_at":"2026-08-03T23:45:53.300961Z","submitted_at":"2024-03-18T11:19:37Z","title":"HDLdebugger: Streamlining HDL debugging with Large Language Models","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2403.11671","snapshot_observed_at":"2026-08-06T15:19:53.469553Z","title":"Hdldebugger: Streamlining hdl debugging with large language models,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":21,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:53.469553Z"},"links":{"cited_paper":"/paper/2403.11671","citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:c1a54fce31b95bec44ebb6d83c21c870291bc180ed4d61f53d1c332b1f0a4960","observation_id":"77b36558-44ef-4312-80e1-243e94660b8f","resolution":{"observed_at":"2026-08-06T15:19:53.469553Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T15:19:57.615620Z","title":"On the viability of using llms for sw/hw co-design: An example in designing cim dnn accelerators,","venue":null,"work_id":"1f7e948a-49c8-453b-97d6-1053d0f26d8e","year":2023},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:53.540972Z"},"links":{"citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:2719fc78359f194004e44e723c8e2e73d93ac9106195fdc3a53c299ea271ffad","observation_id":"3c5f401a-c160-47eb-b04e-921338f3b4f0","resolution":{"observed_at":"2026-08-06T15:19:57.619516Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T15:19:57.605560Z","title":"Openllm-rtl: Open dataset and benchmark for llm-aided design rtl generation,","venue":null,"work_id":"d9eb74a7-fd8e-4ea1-8c50-378216776220","year":2024},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":23,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:53.598888Z"},"links":{"citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:c6c2ebf0bbe77679c937d82413b1b39f078ce036644f1fd54bddc9d3506dc874","observation_id":"f5d9dae5-a761-42cf-800c-74d209fe6d33","resolution":{"observed_at":"2026-08-06T15:19:57.608764Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T15:19:57.590662Z","title":"Benchmarking large language models for auto- mated verilog rtl code generation,","venue":null,"work_id":"7d1365c5-1490-47f2-9e0b-821cb92ab5f3","year":2023},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":24,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:53.661400Z"},"links":{"citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:97bc9df0bb549a2d740d38cd831736aa74ef8f474ab16efa0364f9f373dd9502","observation_id":"74cf41ff-4a09-42b7-8aae-c6711260d67c","resolution":{"observed_at":"2026-08-06T15:19:57.595255Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T15:19:53.739533Z","title":"Verilogeval: Evaluating large language models for verilog code generation,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":25,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:53.739533Z"},"links":{"citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:6385f8f1fd740fa06dde2d05ed7a57321bd58b80129deab337633e585b978b00","observation_id":"2ef22331-e5e6-4600-8290-0bd3f09c9679","resolution":{"observed_at":"2026-08-06T15:19:53.739533Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T15:19:53.804528Z","title":"Rtllm: An open-source benchmark for design rtl generation with large language model,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":26,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:53.804528Z"},"links":{"citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:f441f700cb88a04538d55f9f2769015e7a1fd73caf4e243c19e9265f47f76167","observation_id":"4914d012-6f91-45e8-bfad-ab0f0c13345e","resolution":{"observed_at":"2026-08-06T15:19:53.804528Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2407.08473","last_updated":"2024-07-11T13:10:09Z","snapshot_observed_at":"2026-07-06T18:44:49.512236Z","submitted_at":"2024-07-11T13:10:09Z","title":"Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation","version":1},"cited_work":{"arxiv_id":"2407.08473","doi":null,"metadata_source":"pith","pith_arxiv_id":"2407.08473","snapshot_observed_at":"2026-08-06T15:19:55.464670Z","title":"Natural language is not enough: Benchmarking multi-modal generative AI for Verilog generation","venue":"cs.AR","work_id":"c6b68c57-0e53-4e4a-b520-b363c5500fc9","year":2024},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":27,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:53.881565Z"},"links":{"cited_paper":"/paper/2407.08473","citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:279499b5a1580230f20e9cec0e619ecfdbd14d1cc7736966c7f67fff14a14baf","observation_id":"70bde7e2-afaf-4939-b64b-2e0c5d52b1d5","resolution":{"observed_at":"2026-08-06T15:19:55.561303Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2408.11053","last_updated":"2025-02-03T19:29:27Z","snapshot_observed_at":"2026-07-06T19:03:39.672411Z","submitted_at":"2024-08-20T17:58:56Z","title":"Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2408.11053","snapshot_observed_at":"2026-08-06T15:19:53.956140Z","title":"Revisiting verilogeval: Newer llms, in-context learning, and specification-to-rtl tasks,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":28,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:53.956140Z"},"links":{"cited_paper":"/paper/2408.11053","citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:924f77daccf3c795ec921db2206800306f204bbaa13a02474d0bd1348d95ad31","observation_id":"e3599c72-cd69-4338-945a-42a057a0a49a","resolution":{"observed_at":"2026-08-06T15:19:53.956140Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2405.17378","last_updated":"2024-05-27T17:36:01Z","snapshot_observed_at":"2026-08-06T13:35:45.362718Z","submitted_at":"2024-05-27T17:36:01Z","title":"RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2405.17378","snapshot_observed_at":"2026-08-06T15:19:54.045629Z","title":"Rtl-repo: A benchmark for evaluating llms on large-scale rtl design projects,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":29,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:54.045629Z"},"links":{"cited_paper":"/paper/2405.17378","citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:a04bde25343ef4f3f2a50dede6e40b2725326c2e432a744112f93781de38304b","observation_id":"69825b9b-10e1-41a3-a31a-afc7b65cc0fb","resolution":{"observed_at":"2026-08-06T15:19:54.045629Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2401.13266","last_updated":"2024-01-24T07:13:03Z","snapshot_observed_at":"2026-07-06T17:19:44.130417Z","submitted_at":"2024-01-24T07:13:03Z","title":"SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2401.13266","snapshot_observed_at":"2026-08-06T15:19:54.115981Z","title":"Specllm: Exploring generation and review of vlsi design specification with large language model,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":30,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:54.115981Z"},"links":{"cited_paper":"/paper/2401.13266","citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:c45d5e9bc29240a25d4b210bae41ea33a1a1a38d17a0abc36debc270e8f077c7","observation_id":"164bc178-8406-4244-9429-7df1ac1ac970","resolution":{"observed_at":"2026-08-06T15:19:54.115981Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T15:19:57.565570Z","title":"Opencores: Open source ip-cores,","venue":null,"work_id":"0521d59b-06a0-4f94-be15-e1668af77278","year":null},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":31,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:54.189177Z"},"links":{"citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:70863218103757f6b84813df007a8cf0d2dd3102d4bc6209c3ca13dead6cd8c2","observation_id":"ff7979a1-c519-46e2-a392-2e931d17a6bb","resolution":{"observed_at":"2026-08-06T15:19:57.569393Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T15:19:57.332504Z","title":"Design sdc mmc controller,","venue":null,"work_id":"94c5a086-7d28-4057-ac96-1d7fab03696f","year":null},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":32,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:54.264867Z"},"links":{"citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:7b7f3ab7ea0fc9b3892d590c3b650fe4d2075ade8723f561362e7e4c2e8fe09a","observation_id":"c62f06c9-9c33-43ac-96fc-b9f66e5ea6d7","resolution":{"observed_at":"2026-08-06T15:19:57.437337Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T15:19:57.246897Z","title":"Hummingbirdv2 e203 core and soc,","venue":null,"work_id":"0b10654d-7f46-4b1b-8504-f56add1b617c","year":null},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":33,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:54.327434Z"},"links":{"citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:b466a18f6a65841e103d119e5310ea6506fa591e942c0ee706b5de69e668af71","observation_id":"e43d6337-039e-41c9-8b86-a617daf1885c","resolution":{"observed_at":"2026-08-06T15:19:57.280192Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T15:19:57.139136Z","title":"SWE-bench: Can language models resolve real- world github issues?","venue":null,"work_id":"652a7fd8-bd49-456a-8b44-0520490257f6","year":2024},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":34,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:54.367139Z"},"links":{"citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:23af25a910eaa74e674916913ea308743ed51d6595c961677f0b9b284a283142","observation_id":"dc751b16-581a-426d-ae31-beb79bd0e116","resolution":{"observed_at":"2026-08-06T15:19:57.180563Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T15:19:57.024840Z","title":"Swe-agent: Agent-computer interfaces enable automated soft- ware engineering,","venue":null,"work_id":"ea4872d8-f04d-4704-b747-3af9e31e92de","year":2024},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":35,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:54.425204Z"},"links":{"citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:18fbe59f165ca2f1af66838048bd34f050b90acc05af1e8ba35fd1cec113b331","observation_id":"44754cb2-12c0-431e-856d-d520d8fc0518","resolution":{"observed_at":"2026-08-06T15:19:57.061380Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T15:19:54.506417Z","title":"Yosys open synthesis suite,","venue":null,"work_id":null,"year":null},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":36,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:54.506417Z"},"links":{"citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:93e3c1f77f5408735bd6b31998e5da5ef00130f4fd969f4a1d8b919f68e8f042","observation_id":"e3463531-c245-4b87-86d5-3012d1a36851","resolution":{"observed_at":"2026-08-06T15:19:54.506417Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T15:19:56.822078Z","title":"Nangate freepdk45 generic open cell library,","venue":null,"work_id":"c2046a30-fc3e-4c93-90e1-e50564f7338c","year":null},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":37,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:54.592098Z"},"links":{"citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:6f54677844fc24997a2c76ddbf8e5346f8d46b36bae3adb764d60b06d2e20a7a","observation_id":"e9ed99ff-8f02-4ea6-92fd-ee7288543b8b","resolution":{"observed_at":"2026-08-06T15:19:56.973350Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T15:19:56.608704Z","title":"Jasper formal verification platform,","venue":null,"work_id":"3dc3e28e-feac-4cdd-a4d1-cd45a50e967d","year":null},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":38,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:54.664749Z"},"links":{"citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:55367758a309a3592639b8f214d25ca1f22a9b234295b95ff2176014dcecced8","observation_id":"68b5ae03-b93a-4182-8732-ca788ceeb595","resolution":{"observed_at":"2026-08-06T15:19:56.720897Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T15:19:54.717596Z","title":"Rouge: A package for automatic evaluation of summaries,","venue":null,"work_id":null,"year":2004},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":39,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:54.717596Z"},"links":{"citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:048fc4f19ad936216004975f5fbedd78b9fb828e9d80bc81b9ff2d8c57cadd26","observation_id":"38d239eb-a80e-4096-99ed-272106e1f5b4","resolution":{"observed_at":"2026-08-06T15:19:54.717596Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2407.21783","last_updated":"2024-11-23T23:27:33Z","snapshot_observed_at":"2026-07-06T18:55:11.576666Z","submitted_at":"2024-07-31T17:54:27Z","title":"The Llama 3 Herd of Models","version":3},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2407.21783","snapshot_observed_at":"2026-08-06T15:19:54.786546Z","title":"The llama 3 herd of models,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":40,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:54.786546Z"},"links":{"cited_paper":"/paper/2407.21783","citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:b0a37c7012442a20b33664d602fe69f84c49408247f802cd822f6f2e6738e683","observation_id":"5771d6d3-c8ba-4519-9fbb-591465b88489","resolution":{"observed_at":"2026-08-06T15:19:54.786546Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2412.19437","last_updated":"2025-02-18T17:26:38Z","snapshot_observed_at":"2026-07-06T02:11:23.670680Z","submitted_at":"2024-12-27T04:03:16Z","title":"DeepSeek-V3 Technical Report","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2412.19437","snapshot_observed_at":"2026-08-06T15:19:54.833135Z","title":"Deepseek-v3 technical report,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":41,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:54.833135Z"},"links":{"cited_paper":"/paper/2412.19437","citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:6f0172266f32dd06517cb763a27b28764eef2995417c1bd677a4611872f265e5","observation_id":"3f831038-4107-4e2e-b847-862962dda043","resolution":{"observed_at":"2026-08-06T15:19:54.833135Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2501.12948","last_updated":"2026-01-04T03:57:36Z","snapshot_observed_at":"2026-07-06T02:11:23.670680Z","submitted_at":"2025-01-22T15:19:35Z","title":"DeepSeek-R1: Incentivizing Reasoning Capability in LLMs via Reinforcement Learning","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2501.12948","snapshot_observed_at":"2026-08-06T15:19:54.912345Z","title":"Deepseek-r1: Incentivizing reasoning capability in llms via reinforcement learning,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":42,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:54.912345Z"},"links":{"cited_paper":"/paper/2501.12948","citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:650fcc9780bc1bd7241f0a299e69e44e5f48c076b60c44333f461aa530d6c096","observation_id":"c8b5081e-dfd5-4581-bb95-209f331f682f","resolution":{"observed_at":"2026-08-06T15:19:54.912345Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2401.14196","last_updated":"2024-01-26T09:23:11Z","snapshot_observed_at":"2026-08-06T22:40:28.707813Z","submitted_at":"2024-01-25T14:17:53Z","title":"DeepSeek-Coder: When the Large Language Model Meets Programming -- The Rise of Code Intelligence","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2401.14196","snapshot_observed_at":"2026-08-06T15:19:54.984124Z","title":"Deepseek-coder: When the large language model meets programming–the rise of code intelligence,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":43,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:54.984124Z"},"links":{"cited_paper":"/paper/2401.14196","citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:0b8b62d2745ed36295e29487d2075e4a0531619f5e3d291dc37ce2a838d5dde8","observation_id":"11d5ca7b-4e07-4288-a55b-97fa15e54d5a","resolution":{"observed_at":"2026-08-06T15:19:54.984124Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T15:19:56.368178Z","title":"Code with codeqwen1.5,","venue":null,"work_id":"13713d53-6252-4873-9cf3-76ab56fa8abe","year":2024},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":44,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:55.078715Z"},"links":{"citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:331dbab5f412ca657c4691e4522ace36a8601e8978f95cfe57021a9906cc3b17","observation_id":"562fdfe4-ca48-4bd7-9bad-1b5e0fbccdd0","resolution":{"observed_at":"2026-08-06T15:19:56.466583Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T15:19:56.137471Z","title":"Verilogcoder: Autonomous verilog coding agents with graph-based planning and abstract syntax tree (ast)- based waveform tracing tool,","venue":null,"work_id":"20d12cc3-0bb5-4da4-904c-fde29b3e86d6","year":2025},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":45,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:55.136895Z"},"links":{"citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:5d879777a15cd8bef14b2b9b195ea8d61e0bc00c3bf4a37cb17061f6eabf43bb","observation_id":"e6a1d32f-c693-4ffd-9adb-0db668c8b1a0","resolution":{"observed_at":"2026-08-06T15:19:56.245402Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2307.09288","last_updated":"2023-07-19T17:08:59Z","snapshot_observed_at":"2026-08-02T11:57:18.735747Z","submitted_at":"2023-07-18T14:31:57Z","title":"Llama 2: Open Foundation and Fine-Tuned Chat Models","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2307.09288","snapshot_observed_at":"2026-08-06T15:19:55.232675Z","title":"Llama 2: Open foundation and fine-tuned chat models,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":46,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:55.232675Z"},"links":{"cited_paper":"/paper/2307.09288","citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:5e24284badaf309023c396613bedeb6b09df635dc194f37f29c4233bb48b6306","observation_id":"69bf2f45-e1a5-4818-9561-54b6a2899556","resolution":{"observed_at":"2026-08-06T15:19:55.232675Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-06T15:19:56.005706Z","title":"Origen: Enhancing rtl code generation with code-to-code augmentation and self-reflection,","venue":null,"work_id":"83f11cbe-26cf-4f2e-a61f-3842ce3d6ac3","year":2024},"citing_paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs","version":1},"reference_index":47,"source":"pdf_text","source_observed_at":"2026-08-06T15:19:55.293263Z"},"links":{"citing_paper":"/paper/2507.16200"},"observation_digest":"sha256:8541c9a1d33f08a7b060cae618a52799298fa6f71c68b89bf3f9be9768fbb61b","observation_id":"fd8bec0f-44b0-480b-a69f-23a536e1145e","resolution":{"observed_at":"2026-08-06T15:19:56.062369Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}}],"paper":{"arxiv_id":"2507.16200","last_updated":"2025-07-22T03:29:23Z","latest_version":1,"primary_category":"cs.LG","snapshot_observed_at":"2026-08-06T15:13:16.621566Z","submitted_at":"2025-07-22T03:29:23Z","title":"RealBench: Benchmarking Verilog Generation Models with Real-World IP Designs"},"reference_resolution":{"displayed":47,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":27,"verified_exact":2,"verified_fuzzy":18},"total_outbound_references":47},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"thesis":"As of 7 August 2026, this Paper Citation Record lists 47 of 47 outbound references and 6 inbound Pith citation observations for arXiv:2507.16200."}