{"as_of":"2026-08-07T22:14:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:f8deb4726b40edc5fd97b66e21572a066ee170231938609070fd91de96f3a7c6","coverage":[{"denominator":46,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":46,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-05T15:17:26.738977Z","state":"measured"},{"denominator":49,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":49,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-07T06:34:17.273281+00:00","state":"measured"},{"denominator":3,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":3,"source":"paper_references, paper_reference_links","source_observed_at":"2026-05-10T10:34:03.353104Z","state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"arxiv_reference","source_observed_at":"2026-05-12T10:01:29.103486Z","state":"measured"}],"external_citation_measurements":[],"inbound":[{"citation":{"cited_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"cited_work":{"arxiv_id":"2508.20030","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"2508.20030","snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Large language models (llms) for electronic design automation (eda)","venue":null,"work_id":"58a883a3-a25d-4ed4-ad67-c818a22d7f3b","year":2025},"citing_paper":{"arxiv_id":"2604.15001","last_updated":"2026-04-17T09:58:55Z","snapshot_observed_at":"2026-07-06T23:02:40.364114Z","submitted_at":"2026-04-16T13:26:52Z","title":"COEVO: Co-Evolutionary Framework for Joint Functional Correctness and PPA Optimization in LLM-Based RTL Generation","version":2},"reference_index":38,"source":"pdf_text","source_observed_at":"2026-05-10T10:34:03.353104Z"},"links":{"cited_paper":"/paper/2508.20030","citing_paper":"/paper/2604.15001"},"observation_digest":"sha256:7073fee1212a15ec443b8cdb6e4b20ea361dabc309c38f0baaa4696ffd13a176","observation_id":"6ee89b98-2128-44f2-bf75-49254f3d57c4","resolution":{"observed_at":"2026-05-10T10:34:28.934689Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"cited_work":{"arxiv_id":"2508.20030","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"2508.20030","snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Large language models (llms) for electronic design automation (eda)","venue":null,"work_id":"58a883a3-a25d-4ed4-ad67-c818a22d7f3b","year":2025},"citing_paper":{"arxiv_id":"2604.27780","last_updated":"2026-04-30T12:19:40Z","snapshot_observed_at":"2026-07-06T23:13:11.623453Z","submitted_at":"2026-04-30T12:19:40Z","title":"RuC: HDL-Agnostic Rule Completion Benchmark Generation","version":1},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-05-07T08:16:15.514823Z"},"links":{"cited_paper":"/paper/2508.20030","citing_paper":"/paper/2604.27780"},"observation_digest":"sha256:9cfad9160120297ab9a62a4a3c38a8ac7c8fba9d6121202f488339afa434ac1e","observation_id":"d77cd7ef-91b1-4921-92eb-55d908ba70c2","resolution":{"observed_at":"2026-05-12T10:01:29.106169Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"cited_work":{"arxiv_id":"2508.20030","doi":null,"metadata_source":"arxiv_reference","pith_arxiv_id":"2508.20030","snapshot_observed_at":"2026-06-05T21:23:00.469572Z","title":"Large language models (llms) for electronic design automation (eda)","venue":null,"work_id":"58a883a3-a25d-4ed4-ad67-c818a22d7f3b","year":2025},"citing_paper":{"arxiv_id":"2605.02285","last_updated":"2026-05-04T07:19:48Z","snapshot_observed_at":"2026-08-02T21:49:54.214629Z","submitted_at":"2026-05-04T07:19:48Z","title":"Complexity Horizons of Compressed Models in Analog Circuit Analysis","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-05-09T16:37:05.972866Z"},"links":{"cited_paper":"/paper/2508.20030","citing_paper":"/paper/2605.02285"},"observation_digest":"sha256:abf74e8a76a42e36014a80e8ff5c2516332d2f04c8a9e6e731c9673cc56d80c3","observation_id":"e28b0c69-df05-4cc0-a702-dcec3f3cae0a","resolution":{"observed_at":"2026-05-11T16:31:06.383281Z","resolver_source":"arxiv_id","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}}],"links":{"evidence":"/evidence","html":"/paper/2508.20030/citation-record","integrity":"/paper/2508.20030/integrity","json":"/paper/2508.20030/citation-record.json","paper":"/paper/2508.20030"},"outbound":[{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:27.502122Z","title":"Machine Learning in Advanced IC Design: A Methodological Survey,","venue":null,"work_id":"e45c9dad-6150-4131-a758-65530a01841e","year":2023},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.405209Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:28592c0c2bde23ee73eb9dfda4abdbb96f3d68ed506793c7696c8e4124d85018","observation_id":"e8fe83bf-3eb5-4de7-9d62-06227034e378","resolution":{"observed_at":"2026-08-05T15:17:27.507356Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:27.486872Z","title":"Chip-Chat: Chal- lenges and Opportunities in Conversational Hardware Design,","venue":null,"work_id":"22a9b6b5-7c90-4d9b-aa77-8393cde6227a","year":2023},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.410571Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:2d666f74c50da1aaedcdf01d325ea0101b316cfbf9e1a0d8787ee02e76823184","observation_id":"1848e6a9-dfe8-4ec4-aa43-457cc378d63c","resolution":{"observed_at":"2026-08-05T15:17:27.491849Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:27.472075Z","title":"Rome was Not Built in a Single Step: Hierarchical Prompting for LLM-based Chip Design,","venue":null,"work_id":"ce60136e-9f24-419e-8a2e-000a5d97da4d","year":2024},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.415973Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:c04f0a66099306ad1840336098765574ad2dd1c472458c5eb11c685c67b12830","observation_id":"d4445a67-ee2a-41a6-96e8-5e6efdbf4929","resolution":{"observed_at":"2026-08-05T15:17:27.476637Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:27.457323Z","title":"Benchmarking Large Language Models for Automated Verilog RTL Code Generation,","venue":null,"work_id":"c6442e9e-bde3-4181-97b8-dc09c03f73c8","year":2023},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.422189Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:ccbccc41d891291c28d2342d1a42fa3e7abc691de93f35fef5060ff98e8fc2fd","observation_id":"2c886117-4070-4b0a-9cfa-53827812f1c3","resolution":{"observed_at":"2026-08-05T15:17:27.462068Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:27.442698Z","title":"Large Language Models for Verification, Testing, and Design,","venue":null,"work_id":"9d4bba6b-3138-4dee-9a47-ccb7b7de7cb4","year":2025},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.428721Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:1661bb66d3e8ed5ae3d2d30b5e6e5db1b94f66c7ed7c2f931e94aad62f190ee9","observation_id":"f8b08a33-32ab-4051-95a7-41e529a6603a","resolution":{"observed_at":"2026-08-05T15:17:27.447016Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2410.18582","last_updated":"2024-10-24T09:35:21Z","snapshot_observed_at":"2026-07-06T19:38:57.409491Z","submitted_at":"2024-10-24T09:35:21Z","title":"LLM-Aided Efficient Hardware Design Automation","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2410.18582","snapshot_observed_at":"2026-08-05T15:17:26.433569Z","title":"LLM-Aided Efficient Hardware Design Automation,","venue":null,"work_id":null,"year":null},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.433569Z"},"links":{"cited_paper":"/paper/2410.18582","citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:40143ee0e71c9829dafbef471a31ceddcb86430ceecf7b4dc6919af4b4d8a957","observation_id":"db8c42d3-45c7-490f-8ad5-cf0c8f555ad0","resolution":{"observed_at":"2026-08-05T15:17:26.433569Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2401.13266","last_updated":"2024-01-24T07:13:03Z","snapshot_observed_at":"2026-07-06T17:19:44.130417Z","submitted_at":"2024-01-24T07:13:03Z","title":"SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2401.13266","snapshot_observed_at":"2026-08-05T15:17:26.438693Z","title":"SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.438693Z"},"links":{"cited_paper":"/paper/2401.13266","citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:775e1beb1de68882f1c44209261fe735a7835f55016bab2dd5a7b6782dcaddf8","observation_id":"59cc461e-139d-4582-a677-eb7db571b308","resolution":{"observed_at":"2026-08-05T15:17:26.438693Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:27.428229Z","title":"Automatically Improving LLM-based Verilog Generation using EDA Tool Feedback,","venue":null,"work_id":"ec8bab1a-b17a-4df9-86ad-4e4f62d944a5","year":2025},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.443926Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:8fcc102e3fe8d3998d7462ed5528889bf02b345b30aefe9612b7598b9b042952","observation_id":"2b195d48-a7b4-4bca-92be-81470df74bf1","resolution":{"observed_at":"2026-08-05T15:17:27.433018Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:27.412871Z","title":"GPT4AIGChip: Towards Next-Generation AI Accelerator Design Automation via Large Language Models,","venue":null,"work_id":"e9d3a21a-52fe-4540-a262-131adbc88c11","year":2023},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.448310Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:c4732699ccd0176b67bedc922adc04a6434e939422d6eac8fbdedc894b6112e3","observation_id":"5566a2f8-2ba0-427d-ab6b-64fbf1129e1e","resolution":{"observed_at":"2026-08-05T15:17:27.417856Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:27.398628Z","title":"Evaluating LLMs for Hardware Design and Test,","venue":null,"work_id":"5b7f6ed4-d3c7-4e06-987a-7cb870a18937","year":2024},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.452909Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:69dda864c736fef72fe017f59ff774aba0ecdd4fdf8a4d589a5ef58f34bf92f6","observation_id":"197eb328-ffd5-4b71-8920-16d863232994","resolution":{"observed_at":"2026-08-05T15:17:27.403087Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:27.384420Z","title":"Customized Retrieval Augmented Generation and Benchmarking for EDA Tool Documentation QA,","venue":null,"work_id":"f9c9552c-2df6-4113-a74b-db85d6247054","year":2024},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.457807Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:4a86b3e637b0fb2f8a5d2656c5ad0729048728b4e5ac905fa5fbdb8e510a6caf","observation_id":"e1ded366-1d33-4ff3-a18a-a2ebf109f7aa","resolution":{"observed_at":"2026-08-05T15:17:27.389063Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:27.369285Z","title":"FPGA HLS Today: Successes, Challenges, and Opportunities,","venue":null,"work_id":"940554b5-d818-42be-bf53-7b9254cae04a","year":2022},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.463108Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:f14a3110e4c8139117694b75bfaa42375d744a0841a8572807b0844e93a05f2a","observation_id":"5b0da748-671e-4b30-b3be-31e20e985e2e","resolution":{"observed_at":"2026-08-05T15:17:27.374256Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:27.354222Z","title":"New solutions on LLM acceleration, optimization, and application,","venue":null,"work_id":"1bc12c1f-3f8f-43d7-904c-2e178f2c42ac","year":2024},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.467630Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:05937c593984f617f83260460c60971887226d22a4b027df2389b36c2d076acd","observation_id":"21cedfed-5a4b-47a5-a221-aee043d2ee64","resolution":{"observed_at":"2026-08-05T15:17:27.359115Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:27.339472Z","title":"VRank: Enhancing Verilog Code Generation from Large Lan- guage Models via Self-Consistency,","venue":null,"work_id":"53c86632-b70c-405c-843f-4b28cb9555e1","year":2025},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.472529Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:3cf6a454cd8ee9eec05dac6499e8280d83dad66f19c9f7652d5c5e18f9497a30","observation_id":"305f778f-b4ef-4f83-8fe2-7b839f6ff09f","resolution":{"observed_at":"2026-08-05T15:17:27.344731Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:27.323696Z","title":"VFocus: Better Verilog Generation from Large Language Model via Focused Reasoning,","venue":null,"work_id":"463c80d3-908e-4359-9d69-9fb1cee8d334","year":2025},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.476683Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:be4f153e9a39dfcf0b84422baf86c57acf094a09186a262897e435576decc77f","observation_id":"26c90166-46b4-4138-98e4-fdcb498b82eb","resolution":{"observed_at":"2026-08-05T15:17:27.328717Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2311.16543","last_updated":"2024-05-20T19:50:06Z","snapshot_observed_at":"2026-08-04T21:40:37.585486Z","submitted_at":"2023-11-28T06:18:54Z","title":"RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models","version":3},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.16543","snapshot_observed_at":"2026-08-05T15:17:26.480901Z","title":"RTLFixer: Automatically Fixing RTL Syntax Errors with Large Language Models,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.480901Z"},"links":{"cited_paper":"/paper/2311.16543","citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:5d81b2c838b3819ad7ce2ba29808e9b42744e3c97ac7ccfa09be79877a30c203","observation_id":"e505c0ee-6cec-4b82-8693-d88db663b769","resolution":{"observed_at":"2026-08-05T15:17:26.480901Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:27.307563Z","title":"C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap,","venue":null,"work_id":"d57fe965-09a4-433f-bc08-821e2dfab77b","year":2025},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.485850Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:4eebf0c8a43b1ad46b1270ad2cc4547b4dba0721caed8594fa7756f7bc5b2ece","observation_id":"243a7da4-b2bc-44a2-820a-4ef371a6f542","resolution":{"observed_at":"2026-08-05T15:17:27.312653Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:27.290444Z","title":"AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design,","venue":null,"work_id":"42cd7c98-1224-4905-ba6a-9d0cab360230","year":2024},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.490493Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:7f807d6ed3175368ae6f9d4f8b4e80037679442b89cad0b22f2151c93a349f39","observation_id":"0bed9af1-b5e4-4777-96c6-a819ca385c15","resolution":{"observed_at":"2026-08-05T15:17:27.295784Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:27.273530Z","title":"CorrectBench: Automatic Testbench Generation with Functional Self- correction Using LLMs for HDL Design,","venue":null,"work_id":"48cad8e5-fe66-44e6-8473-15b8aab8f64d","year":2025},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.495068Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:d5edc73af18f163db12936be042061a99de4b6d89099946cc0d641cc45858568","observation_id":"23d91cde-3c06-43c4-9652-0cc71c75b439","resolution":{"observed_at":"2026-08-05T15:17:27.278290Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:27.256684Z","title":"AssertLLM: Generating Hardware Verification Assertions from Design Speci- fications via Multi-LLMs,","venue":null,"work_id":"7f873bbb-3c82-4f8f-a134-0a0c397c9789","year":2024},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.609999Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:605731d39feb462c362fa62fc3558a0ecb8af5e4e8fa7d51aceb946ccfb99149","observation_id":"fd249cee-20f9-42d1-b9ed-ab45197dc072","resolution":{"observed_at":"2026-08-05T15:17:27.262090Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:27.238460Z","title":"LLSM: LLM-enhanced Logic Synthesis Model with EDA-guided CoT Prompting,","venue":null,"work_id":"2cb707f7-0633-4617-a984-b1f913e9f205","year":2024},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.619759Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:3dc4694b5681e76b26ddcd4056640b3f866964da39b46fe262f3b576b0eff253","observation_id":"8a93b953-1687-4bc9-b001-ba1b376e761b","resolution":{"observed_at":"2026-08-05T15:17:27.244586Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2312.01022","last_updated":"2024-01-09T12:36:49Z","snapshot_observed_at":"2026-07-06T16:55:57.634861Z","submitted_at":"2023-12-02T04:14:23Z","title":"Advanced Large Language Model (LLM)-Driven Verilog Development: Enhancing Power, Performance, and Area Optimization in Code Synthesis","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2312.01022","snapshot_observed_at":"2026-08-05T15:17:26.624466Z","title":"Advanced LLM-Driven Verilog Development: Enhancing Power, Performance, and Area Optimization in Code Synthesis,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":23,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.624466Z"},"links":{"cited_paper":"/paper/2312.01022","citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:322905b4149fcebeaf3e85ad3cfd696de7e736f49cd4351e71a5e841f859e5de","observation_id":"a593338a-4518-4f66-96ef-62f9f47d3da3","resolution":{"observed_at":"2026-08-05T15:17:26.624466Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:27.219525Z","title":"VeriOpt: PPA-Aware High-Quality Verilog Generation via Multi- Role LLMs,","venue":null,"work_id":"758f7b6e-41d0-4c9c-ac95-4508a10185b3","year":2025},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":24,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.629321Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:c5b954313ad9706476985cc71c7d336593a3f6b19502b1226f3fcce7fab43030","observation_id":"622b5ae1-10a0-4a8b-84c6-ebddea190250","resolution":{"observed_at":"2026-08-05T15:17:27.225568Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2309.09437","last_updated":"2023-09-28T15:27:39Z","snapshot_observed_at":"2026-08-06T10:04:18.383733Z","submitted_at":"2023-09-18T02:37:43Z","title":"Using LLMs to Facilitate Formal Verification of RTL","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2309.09437","snapshot_observed_at":"2026-08-05T15:17:26.633827Z","title":"MCP4EDA: LLM-Powered Model Context Protocol RTL-to-GDSII Automation with Backend Aware Synthesis Optimization,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":25,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.633827Z"},"links":{"cited_paper":"/paper/2309.09437","citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:4836b98165a988973d9c5c30fd2178e95d8a2899d2861a719f3896fd727cccd5","observation_id":"845a783f-10c2-42d6-8e14-7da68ed15ad7","resolution":{"observed_at":"2026-08-05T15:17:26.633827Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:27.202076Z","title":"LayoutCopilot: An LLM-powered Multi-agent Collaborative Framework for Interactive Analog Layout Design,","venue":null,"work_id":"44714551-d5aa-4683-9d57-47969f881b48","year":2025},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":26,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.637992Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:91f6b69baa708ed3b3d69f91b894a75bc57789ca4ec59f7e644ffd314bea8030","observation_id":"9f8d5cad-9880-4dd3-b71f-cd36b55053f1","resolution":{"observed_at":"2026-08-05T15:17:27.207240Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:27.185475Z","title":"HLSRewriter: Efficient Refactoring and Optimization of C/C++ Code with LLMs for High-Level Synthesis,","venue":null,"work_id":"ae23eebc-9fc5-469f-899d-8f416cb62825","year":2024},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":27,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.642466Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:19e7b27b2fb8de2bc16a5276f35c66956bc1e2814b83cb1fa24ad06c5e5e837c","observation_id":"1e8765c3-a4f3-4826-8e93-28063b7d37db","resolution":{"observed_at":"2026-08-05T15:17:27.190946Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:27.169088Z","title":"Automated C/C++ Program Repair for High-Level Synthesis via Large Language Models,","venue":null,"work_id":"556d8a65-c8ec-41ad-b219-3f6b06aac0e7","year":2024},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":28,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.647366Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:69ce8be45a67e4a2991b89bead539c8c902b9ba09f916c86bf04a3907e50bb26","observation_id":"54060301-5aec-4634-b91b-d7851115fedd","resolution":{"observed_at":"2026-08-05T15:17:27.174209Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:27.153801Z","title":"Logic Design of Neural Networks for High-Throughput and Low- Power Applications,","venue":null,"work_id":"ad4b7297-08be-48cf-bce4-07f094d4c0f5","year":2024},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":29,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.652307Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:d0f8d767c9b6ac6ae6b8d79ac44eb6fbc5825019caea27891a3047faaea60810","observation_id":"f7992068-f325-486c-9965-43773a5d833d","resolution":{"observed_at":"2026-08-05T15:17:27.158538Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:27.135906Z","title":"HLSTester: Efficient Testing of Behavioral Discrepancies with LLMs for High-Level Synthesis,","venue":null,"work_id":"3b8b54b1-b6f5-4f0c-81d8-68adc02af4c1","year":2025},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":30,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.657178Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:028a289cebdd02402946b8606143135c5b669c579a01eb6c04d5eece1b00e3f5","observation_id":"368fb9bd-38fb-4720-801a-eb0012c9ed2b","resolution":{"observed_at":"2026-08-05T15:17:27.141876Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:27.113625Z","title":"Fault Testing and Diagnosis Techniques for Carbon Nanotube-Based FPGAs,","venue":null,"work_id":"d5cde26c-7d97-4d25-bd69-36f76c9e3f4c","year":2022},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":31,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.661775Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:69c4038e838a47abb3c980e745e9711b8481ac52331563a16e79528081b610c4","observation_id":"1b037ca4-f51a-48bd-a102-faa68b28a0cd","resolution":{"observed_at":"2026-08-05T15:17:27.121205Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:27.096303Z","title":"Exploring the Mysteries of System-Level Test,","venue":null,"work_id":"90ef1699-2647-4bc6-a4b6-8c28b47d3bb7","year":2020},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":32,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.666423Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:47879758e2760b80d82b994bd7f2b053b01177f50d0dcf9c8be7b100386d07e6","observation_id":"7b92d796-5e7c-4c2e-ae19-72fd6b209a31","resolution":{"observed_at":"2026-08-05T15:17:27.101857Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:27.079673Z","title":"Beyond structural test, the rising need for system-level test,","venue":null,"work_id":"0abf0e67-2a9c-481d-9bb3-11097929745a","year":2018},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":33,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.670760Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:c8cc52a586e2b792c6aad42a69809e0c0fd0ce03ab0ed60632eff99b312981d1","observation_id":"60543627-7291-4f0a-bb5b-909e0086d026","resolution":{"observed_at":"2026-08-05T15:17:27.084366Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:27.064224Z","title":"Automating Greybox System-Level Test Generation,","venue":null,"work_id":"cf650531-b96e-4832-963c-8af40087337a","year":2023},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":34,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.675783Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:9ea35a2cb96a35d5fe280bc51af29fa7a626e61dd0841ccaca4cadf863339f52","observation_id":"274b7946-66f1-4062-915d-473a56c0a2ab","resolution":{"observed_at":"2026-08-05T15:17:27.069137Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:27.046709Z","title":"Optimizing System-Level Test Program Generation via Genetic Programming,","venue":null,"work_id":"cc7b5aa3-e345-407c-bf0f-6e07ff45fb25","year":2024},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":35,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.680394Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:c8b99897e27e068d3aed2dffa6d2bd36e96fa937abf085c902c5e2c62bd0bdc5","observation_id":"53a8c6e6-5f86-4e16-9983-79d03552e6f1","resolution":{"observed_at":"2026-08-05T15:17:27.052371Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:27.030568Z","title":"SonicBOOM: The 3rd Generation Berkeley Out-of-Order Machine,","venue":null,"work_id":"b7e3edae-55ce-46a3-9de4-bc3b329f4bb8","year":2020},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":36,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.685657Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:78b571c4e7e9460b563cc88574fc2086308ed1d430419dc6176b0835a7413d56","observation_id":"436929b6-2f8c-4634-9a55-c063f456dd77","resolution":{"observed_at":"2026-08-05T15:17:27.035968Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:27.014655Z","title":"Large Language Model-based Optimization for System-Level Test Program Generation,","venue":null,"work_id":"94a9f9e0-79ef-4b31-92bc-2ee1df1c6142","year":2024},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":37,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.690342Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:af8ce6dfa0d770894fbe3244efdb3ec59f459bdcf31916c3c22ceb5290fb65bd","observation_id":"76851747-ad13-4fe6-b29d-818b680be469","resolution":{"observed_at":"2026-08-05T15:17:27.019674Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2305.06599","last_updated":"2023-09-07T11:39:07Z","snapshot_observed_at":"2026-08-03T16:58:05.952045Z","submitted_at":"2023-05-11T06:43:37Z","title":"Structured Chain-of-Thought Prompting for Code Generation","version":3},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2305.06599","snapshot_observed_at":"2026-08-05T15:17:26.694869Z","title":"Structured Chain-of-Thought Prompting for Code Generation,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":38,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.694869Z"},"links":{"cited_paper":"/paper/2305.06599","citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:f86220841f05ca1ddf85ab0718a72fe09917afbffa8443b79978bd89b7e814e4","observation_id":"82b761f9-5b33-4886-9cdc-177c4aee7fda","resolution":{"observed_at":"2026-08-05T15:17:26.694869Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:26.998860Z","title":"DA VE: Deriving Automatically Verilog from English,","venue":null,"work_id":"af43bc77-6873-4243-ab9b-ebc85eeca947","year":2020},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":39,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.700239Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:10847fa9451dc4221009f5cf06a7ea855796be5f20dcb3104735d9b910b6bf44","observation_id":"5b5e979e-216b-48cf-85f5-0f6f7eb0ebc2","resolution":{"observed_at":"2026-08-05T15:17:27.003782Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:26.983651Z","title":"VeriGen: A Large Language Model for Verilog Code Generation,","venue":null,"work_id":"a3799a4b-a1b6-4c50-96c3-025353b57472","year":2024},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":40,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.704485Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:c7862a5e780ed38629121bb2f6f408f3c74c029b06344b3dd80817d9f6362e80","observation_id":"e13a8c6b-16f0-404c-8a7e-928b7912c4ed","resolution":{"observed_at":"2026-08-05T15:17:26.988888Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:26.966550Z","title":"RTLCoder: Fully Open-Source and Efficient LLM-Assisted RTL Code Generation Technique,","venue":null,"work_id":"25656548-fcc9-49b8-81d4-3bce65b93cd3","year":2024},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":41,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.708879Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:477dace9c3a929ff80c02c29588c3993daa2e7d19c4156651495c75e5ea2b26e","observation_id":"fa5e04e6-872e-4480-b868-b1f880fd66e9","resolution":{"observed_at":"2026-08-05T15:17:26.972538Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:26.949884Z","title":"VerilogEval: Evaluating Large Language Models for Verilog Code Generation,","venue":null,"work_id":"b0835a94-98d3-4a3b-8535-c8c1975ef75c","year":2023},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":42,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.714290Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:d3ff2e0237aa4bc0230efbfa8f7e4dd6d5a7171fbd210755b94271075a41a366","observation_id":"49ed47ef-aa8f-4a6e-b99a-2d79d91dc187","resolution":{"observed_at":"2026-08-05T15:17:26.955029Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2407.10424","last_updated":"2025-05-11T07:35:24Z","snapshot_observed_at":"2026-07-06T18:46:14.144689Z","submitted_at":"2024-07-15T03:57:20Z","title":"CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarization","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2407.10424","snapshot_observed_at":"2026-08-05T15:17:26.718735Z","title":"CodeV: Empowering LLMs with HDL Generation through Multi-Level Summarization,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":43,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.718735Z"},"links":{"cited_paper":"/paper/2407.10424","citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:3ac32b730270104957a1046e5e70c611c6c996258426f0e3ad97f7e76f1a136b","observation_id":"011bea9b-692c-4736-9de7-212f8604c569","resolution":{"observed_at":"2026-08-05T15:17:26.718735Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:26.934244Z","title":"LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust,","venue":null,"work_id":"22d26c7d-5128-4f56-b538-0acf5f9959b3","year":2024},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":44,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.724254Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:a25ace870cab1e95b6631e519669cbad6e170b247fe8ec24ba4913a68ae7f5c2","observation_id":"2d812da0-0270-4d07-a1b7-ad4afc4f1288","resolution":{"observed_at":"2026-08-05T15:17:26.939234Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:26.918401Z","title":"Verileaky: Navigating IP Protection vs. Utility in Fine-Tuning for LLM- Driven Verilog Coding,","venue":null,"work_id":"245ffa7a-f3ad-4a29-a885-b2a972b6bf32","year":2025},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":45,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.729118Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:a9fcdd1f777df9e5c00085bce73769dd935231ca4fa83dbe27c58ac88158e4b8","observation_id":"87c45272-1c82-43a2-b626-cd9b8be9e8ce","resolution":{"observed_at":"2026-08-05T15:17:26.923363Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:26.901327Z","title":"RTL-Breaker: Assessing the Security of LLMs Against Backdoor Attacks on HDL Code Generation,","venue":null,"work_id":"2aeee389-1be5-4bb8-9729-b2972dd994b9","year":2025},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":46,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.734121Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:3790a3810741d9bd2c7d4085d7c59f6259574c253b03aa351bfb676ac3687db6","observation_id":"a5b628d2-552b-41c1-bbe0-f4f018179217","resolution":{"observed_at":"2026-08-05T15:17:26.907924Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T15:17:26.882728Z","title":"SALAD: Systematic Assessment of Machine Unlearning on LLM- Aided Hardware Design,","venue":null,"work_id":"38b1d6fa-feb7-4bc0-978c-03b103c24af8","year":2025},"citing_paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)","version":1},"reference_index":47,"source":"pdf_text","source_observed_at":"2026-08-05T15:17:26.738977Z"},"links":{"citing_paper":"/paper/2508.20030"},"observation_digest":"sha256:471136b0e10b1e4d198b7dc03675b7966fbaeb3ea7a106f2a40c5ada17e51a04","observation_id":"27bb073f-8ee5-4835-a368-8c65a38a83f6","resolution":{"observed_at":"2026-08-05T15:17:26.889380Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}}],"paper":{"arxiv_id":"2508.20030","last_updated":"2025-08-27T16:33:51Z","latest_version":1,"primary_category":"eess.SY","snapshot_observed_at":"2026-08-06T07:49:00.648428Z","submitted_at":"2025-08-27T16:33:51Z","title":"Large Language Models (LLMs) for Electronic Design Automation (EDA)"},"reference_resolution":{"displayed":46,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":7,"verified_exact":0,"verified_fuzzy":39},"total_outbound_references":46},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"thesis":"As of 7 August 2026, this Paper Citation Record lists 46 of 46 outbound references and 3 inbound Pith citation observations for arXiv:2508.20030."}