{"as_of":"2026-08-22T07:02:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:90ccc087e191c21d3cc6eaa3e5c3c792c84d4fae1bdd1e34862da7a95a5069ad","coverage":[{"denominator":23,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":23,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-05T14:58:41.191226Z","state":"measured"},{"denominator":23,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":23,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-22T06:32:14.747728+00:00","state":"measured"},{"denominator":0,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"cited_works","source_observed_at":null,"state":"measured"}],"external_citation_measurements":[],"inbound":[],"links":{"evidence":"/evidence","html":"/paper/2508.20653/citation-record","integrity":"/paper/2508.20653/integrity","json":"/paper/2508.20653/citation-record.json","paper":"/paper/2508.20653"},"outbound":[{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T14:58:48.633133Z","title":"Breakthrough aes performance with intel aes new instructions,","venue":null,"work_id":"39391cb0-2136-47f1-ad7e-22feaba57df7","year":2010},"citing_paper":{"arxiv_id":"2508.20653","last_updated":"2025-08-28T10:57:13Z","snapshot_observed_at":"2026-08-14T21:36:25.585559Z","submitted_at":"2025-08-28T10:57:13Z","title":"Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-05T14:58:38.220344Z"},"links":{"citing_paper":"/paper/2508.20653"},"observation_digest":"sha256:678c050e5b4d7907374caa4c79958b62e41e25ae3732a263fd4631d59884051c","observation_id":"509c9db3-e74d-4f41-8643-f1e5651a9340","resolution":{"observed_at":"2026-08-05T14:58:48.733100Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T14:58:48.376458Z","title":"Armv8-a cryptographic extension,","venue":null,"work_id":"08277ec4-6b7c-40a8-8006-58eeed3b2f3c","year":null},"citing_paper":{"arxiv_id":"2508.20653","last_updated":"2025-08-28T10:57:13Z","snapshot_observed_at":"2026-08-14T21:36:25.585559Z","submitted_at":"2025-08-28T10:57:13Z","title":"Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V","version":1},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-05T14:58:38.312118Z"},"links":{"citing_paper":"/paper/2508.20653"},"observation_digest":"sha256:0915a3b3b48ab19c687aec1e3d6b949a88f5d669e094f683ef51f4303154f8ce","observation_id":"baaf82c4-5f04-4b21-be63-df39009df320","resolution":{"observed_at":"2026-08-05T14:58:48.510401Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T14:58:48.049588Z","title":"Lessons learned from designing a 65nm asic for evaluating third round sha-3 candidates,","venue":null,"work_id":"a3a26072-60fb-4d99-bc1d-3b6764293808","year":2012},"citing_paper":{"arxiv_id":"2508.20653","last_updated":"2025-08-28T10:57:13Z","snapshot_observed_at":"2026-08-14T21:36:25.585559Z","submitted_at":"2025-08-28T10:57:13Z","title":"Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V","version":1},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-05T14:58:38.409925Z"},"links":{"citing_paper":"/paper/2508.20653"},"observation_digest":"sha256:9bac9755d433babfec4abef12a9f01ff75a7c424fa0cd4642dc6d84da2499a4a","observation_id":"9baacf33-c092-4421-a504-cb319f2710f4","resolution":{"observed_at":"2026-08-05T14:58:48.218418Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T14:58:45.836998Z","title":"Sha2 and sha-3 accelerator design in a 7 nm technology within the european processor initiative,","venue":null,"work_id":"ef937475-b5b3-46fe-8dc7-c9f41c7b609f","year":2021},"citing_paper":{"arxiv_id":"2508.20653","last_updated":"2025-08-28T10:57:13Z","snapshot_observed_at":"2026-08-14T21:36:25.585559Z","submitted_at":"2025-08-28T10:57:13Z","title":"Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V","version":1},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-05T14:58:38.536119Z"},"links":{"citing_paper":"/paper/2508.20653"},"observation_digest":"sha256:1acffddc4620f07b2723dd0c9e946d45b176eba320074f76e7a9a4c6a0f635e4","observation_id":"1e941771-4f6e-4e37-b90a-1bebc6ee769f","resolution":{"observed_at":"2026-08-05T14:58:47.888535Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T14:58:45.600613Z","title":"Prototyping platform for performance evaluation of sha-3 candidates,","venue":null,"work_id":"86c1bbef-0920-42f7-b372-6fd4d2cb262c","year":2010},"citing_paper":{"arxiv_id":"2508.20653","last_updated":"2025-08-28T10:57:13Z","snapshot_observed_at":"2026-08-14T21:36:25.585559Z","submitted_at":"2025-08-28T10:57:13Z","title":"Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V","version":1},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-08-05T14:58:38.638111Z"},"links":{"citing_paper":"/paper/2508.20653"},"observation_digest":"sha256:f823f13efb03ff4f204181db311c274418c545ea3f9af0be2bf3f6fc3507f09a","observation_id":"dd6bd60c-29a1-4b95-84d7-8309cd8d7119","resolution":{"observed_at":"2026-08-05T14:58:45.704486Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T14:58:45.343979Z","title":"Comparing hardware performance of round 3 sha-3 candidates using multiple hardware architectures in xilinx and altera fpgas,","venue":null,"work_id":"3769d897-45be-4a75-958f-f3fc6a077261","year":2011},"citing_paper":{"arxiv_id":"2508.20653","last_updated":"2025-08-28T10:57:13Z","snapshot_observed_at":"2026-08-14T21:36:25.585559Z","submitted_at":"2025-08-28T10:57:13Z","title":"Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V","version":1},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-05T14:58:38.773954Z"},"links":{"citing_paper":"/paper/2508.20653"},"observation_digest":"sha256:c23ff01b7b67435a5dfbcd6582a33281f949fc9f1d488f1deb6810a5c447e856","observation_id":"ad4f8abe-83d8-4a4e-b13f-2dbbffe82776","resolution":{"observed_at":"2026-08-05T14:58:45.467220Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T14:58:45.045639Z","title":"A sha-3 co-processor for iot applications,","venue":null,"work_id":"44c675a9-c6de-4b75-9b1e-7c227a79fcfa","year":2020},"citing_paper":{"arxiv_id":"2508.20653","last_updated":"2025-08-28T10:57:13Z","snapshot_observed_at":"2026-08-14T21:36:25.585559Z","submitted_at":"2025-08-28T10:57:13Z","title":"Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-05T14:58:38.852639Z"},"links":{"citing_paper":"/paper/2508.20653"},"observation_digest":"sha256:6367669d277c8a5fe269a50184976f8462a6e85fde6e7367dac4be33e6beec76","observation_id":"8b4167d4-620d-43db-bd07-2a620d3f1cac","resolution":{"observed_at":"2026-08-05T14:58:45.177884Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T14:58:44.795129Z","title":"Design exploration of sha-3 asip for iot on a 32-bit risc-v processor,","venue":null,"work_id":"240d3eda-9cc6-4a79-935e-74e15ca59e1c","year":2018},"citing_paper":{"arxiv_id":"2508.20653","last_updated":"2025-08-28T10:57:13Z","snapshot_observed_at":"2026-08-14T21:36:25.585559Z","submitted_at":"2025-08-28T10:57:13Z","title":"Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V","version":1},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-05T14:58:38.980091Z"},"links":{"citing_paper":"/paper/2508.20653"},"observation_digest":"sha256:1272f1cad0a72a358342bb69d37c9ef3302a7bac0e497ca54e37f479b79af3f1","observation_id":"ac054e43-5a73-4ed6-b3b5-fccf374a2cf3","resolution":{"observed_at":"2026-08-05T14:58:44.915840Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T14:58:44.564002Z","title":"Maximizing the potential of custom risc-v vector extensions for speeding up sha-3 hash functions,","venue":null,"work_id":"8acde1f8-01ef-4744-915e-fb30cc0de319","year":2023},"citing_paper":{"arxiv_id":"2508.20653","last_updated":"2025-08-28T10:57:13Z","snapshot_observed_at":"2026-08-14T21:36:25.585559Z","submitted_at":"2025-08-28T10:57:13Z","title":"Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V","version":1},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-05T14:58:39.092954Z"},"links":{"citing_paper":"/paper/2508.20653"},"observation_digest":"sha256:08f72baa96f5637c6567b4cb0edd65a752817cae6288ae9d6c51c1eb014e16f1","observation_id":"d9252da9-9b90-40fd-bfc6-ccd9f79c9d36","resolution":{"observed_at":"2026-08-05T14:58:44.653338Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T14:58:44.351317Z","title":"Enhancing the hardware pipelining optimization technique of the sha-3 via fpga,","venue":null,"work_id":"53526bdb-1857-43a5-b9af-b0e3e7ab6c4b","year":2023},"citing_paper":{"arxiv_id":"2508.20653","last_updated":"2025-08-28T10:57:13Z","snapshot_observed_at":"2026-08-14T21:36:25.585559Z","submitted_at":"2025-08-28T10:57:13Z","title":"Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-05T14:58:39.206703Z"},"links":{"citing_paper":"/paper/2508.20653"},"observation_digest":"sha256:8ed5e9741ec0c181ca8cbd7e7cf8ea5b8d0f3c769a0e088b87b0dcdff48eb708","observation_id":"2ef0772a-0c56-41de-b93f-e74ac4370bf2","resolution":{"observed_at":"2026-08-05T14:58:44.438017Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T14:58:44.087318Z","title":"Investigation of communication overhead of soc lookaside accelerators,","venue":null,"work_id":"6f640802-6889-4e2c-9705-d3ba8df9ca57","year":2023},"citing_paper":{"arxiv_id":"2508.20653","last_updated":"2025-08-28T10:57:13Z","snapshot_observed_at":"2026-08-14T21:36:25.585559Z","submitted_at":"2025-08-28T10:57:13Z","title":"Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V","version":1},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-05T14:58:39.346364Z"},"links":{"citing_paper":"/paper/2508.20653"},"observation_digest":"sha256:a16e9cf8783c45e002e55046f46aadff9e15e1ca9adbfe0c2a09e643ed2de8dc","observation_id":"4b5a317a-aa23-475a-877a-9ec3499f6e8b","resolution":{"observed_at":"2026-08-05T14:58:44.203885Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T14:58:43.784020Z","title":"Implementation of the sha-3 family us- ing avx512 instructions,","venue":null,"work_id":"d7ea2b6d-97dd-42e7-be00-7683efbc51bd","year":2018},"citing_paper":{"arxiv_id":"2508.20653","last_updated":"2025-08-28T10:57:13Z","snapshot_observed_at":"2026-08-14T21:36:25.585559Z","submitted_at":"2025-08-28T10:57:13Z","title":"Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V","version":1},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-05T14:58:39.452838Z"},"links":{"citing_paper":"/paper/2508.20653"},"observation_digest":"sha256:01c16333e4543e84282f4c58ab483609a5fd131e17163d366010527fd5401d8b","observation_id":"14040cf1-2bb1-4b99-8594-2abcc8e0fa65","resolution":{"observed_at":"2026-08-05T14:58:43.957692Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T14:58:43.548640Z","title":"Vector instruction set extensions for efficient computation of keccak,","venue":null,"work_id":"a59b3dcf-86c9-4eb6-a0d1-db01b2079925","year":2017},"citing_paper":{"arxiv_id":"2508.20653","last_updated":"2025-08-28T10:57:13Z","snapshot_observed_at":"2026-08-14T21:36:25.585559Z","submitted_at":"2025-08-28T10:57:13Z","title":"Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V","version":1},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-05T14:58:39.613304Z"},"links":{"citing_paper":"/paper/2508.20653"},"observation_digest":"sha256:11a6e5e163d1dd3c21b85e47bcf8e52d74cd14507e47c20c563357c2679b0eb0","observation_id":"63948008-0b86-4f0a-8ac3-793097621304","resolution":{"observed_at":"2026-08-05T14:58:43.661982Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T14:58:43.286735Z","title":"Fair and com- prehensive performance evaluation of 14 second round sha-3 asic im- plementations,","venue":null,"work_id":"a93e0a5a-1e7b-407f-8cc0-57a89534d304","year":2010},"citing_paper":{"arxiv_id":"2508.20653","last_updated":"2025-08-28T10:57:13Z","snapshot_observed_at":"2026-08-14T21:36:25.585559Z","submitted_at":"2025-08-28T10:57:13Z","title":"Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V","version":1},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-05T14:58:39.736409Z"},"links":{"citing_paper":"/paper/2508.20653"},"observation_digest":"sha256:3eaa3e39ec7b2f57d92ebc34e130e41d380d2e2367bbd39f9af5a2a0300be26b","observation_id":"0626baaf-f3c7-418d-91fb-b723bb1ec0e4","resolution":{"observed_at":"2026-08-05T14:58:43.443713Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T14:58:43.032620Z","title":"Fpga implementations of the round two sha-3 candidates,","venue":null,"work_id":"435ec3be-ff67-419c-9545-8a5dd6ce3873","year":2010},"citing_paper":{"arxiv_id":"2508.20653","last_updated":"2025-08-28T10:57:13Z","snapshot_observed_at":"2026-08-14T21:36:25.585559Z","submitted_at":"2025-08-28T10:57:13Z","title":"Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V","version":1},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-08-05T14:58:39.899855Z"},"links":{"citing_paper":"/paper/2508.20653"},"observation_digest":"sha256:f84a254d6e6316240a0119fadb35e533d34415902d016c29dbfcce5162d7150e","observation_id":"4cf70188-cecf-4a33-b48e-a7e5a2efdfec","resolution":{"observed_at":"2026-08-05T14:58:43.158093Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T14:58:42.777271Z","title":"High performance pipelined fpga implementation of the sha-3 hash algorithm,","venue":null,"work_id":"ee975d7d-0a5d-4c2f-b32b-2de680058a94","year":2015},"citing_paper":{"arxiv_id":"2508.20653","last_updated":"2025-08-28T10:57:13Z","snapshot_observed_at":"2026-08-14T21:36:25.585559Z","submitted_at":"2025-08-28T10:57:13Z","title":"Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V","version":1},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-05T14:58:40.022419Z"},"links":{"citing_paper":"/paper/2508.20653"},"observation_digest":"sha256:e445f39edb51c32fbc39bcb335aa297e74fffe2c6dabe879cbf806ae0e645b96","observation_id":"16702d21-35ed-4cbd-b25a-4ecbf7d5dd82","resolution":{"observed_at":"2026-08-05T14:58:42.896472Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T14:58:42.553189Z","title":"Risc-v cryptography extensions standardisation work,","venue":null,"work_id":"f13bf1fd-fb2b-42dc-957a-60fb9cdb628c","year":null},"citing_paper":{"arxiv_id":"2508.20653","last_updated":"2025-08-28T10:57:13Z","snapshot_observed_at":"2026-08-14T21:36:25.585559Z","submitted_at":"2025-08-28T10:57:13Z","title":"Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-05T14:58:40.162975Z"},"links":{"citing_paper":"/paper/2508.20653"},"observation_digest":"sha256:2904cb09c1e8c08ea7219051967ea9934698ce88b053a85512301e327fc7ed7f","observation_id":"0e2cec78-a055-41a5-b567-acec15bbfd98","resolution":{"observed_at":"2026-08-05T14:58:42.653536Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T14:58:42.359975Z","title":"Keccakcodepackage,","venue":null,"work_id":"51affae0-e27f-47fc-92e0-ba3d6cff17e2","year":null},"citing_paper":{"arxiv_id":"2508.20653","last_updated":"2025-08-28T10:57:13Z","snapshot_observed_at":"2026-08-14T21:36:25.585559Z","submitted_at":"2025-08-28T10:57:13Z","title":"Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V","version":1},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-05T14:58:40.368078Z"},"links":{"citing_paper":"/paper/2508.20653"},"observation_digest":"sha256:be41ac550a9793305d53517600da4103c4bd30e068349468d3d1c44d38c4e747","observation_id":"56949bb9-3086-4656-be64-f463773f5936","resolution":{"observed_at":"2026-08-05T14:58:42.430429Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T14:58:42.075139Z","title":"Cryptographic algorithm validation program: Secure hashing,","venue":null,"work_id":"ae7cc759-c02c-47dc-8c6d-24ea97ae44c8","year":null},"citing_paper":{"arxiv_id":"2508.20653","last_updated":"2025-08-28T10:57:13Z","snapshot_observed_at":"2026-08-14T21:36:25.585559Z","submitted_at":"2025-08-28T10:57:13Z","title":"Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V","version":1},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-08-05T14:58:40.597414Z"},"links":{"citing_paper":"/paper/2508.20653"},"observation_digest":"sha256:97cdce15a7a13170ac50a130987c45465e8e9c26a00bd10df76a8f31c8f9e04f","observation_id":"ea89062e-fe47-44fc-be3a-3cd3ba931081","resolution":{"observed_at":"2026-08-05T14:58:42.178372Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T14:58:41.816826Z","title":"The cost of application-class processing: Energy and performance analysis of a linux-ready 1.7-ghz 64-bit risc- v core in 22-nm fdsoi technology,","venue":null,"work_id":"34d18f99-796a-49b4-afd6-58655b9ead0c","year":2019},"citing_paper":{"arxiv_id":"2508.20653","last_updated":"2025-08-28T10:57:13Z","snapshot_observed_at":"2026-08-14T21:36:25.585559Z","submitted_at":"2025-08-28T10:57:13Z","title":"Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V","version":1},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-08-05T14:58:40.803777Z"},"links":{"citing_paper":"/paper/2508.20653"},"observation_digest":"sha256:88283481f4325be208b228beab60e2717f9faed07107981b107809beaf7d41b1","observation_id":"b9e7e42b-ae04-4d0d-8eef-16a17dc72c6e","resolution":{"observed_at":"2026-08-05T14:58:41.929880Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T14:58:41.639122Z","title":"Risc-v tests,","venue":null,"work_id":"ebd9cbc1-90ab-4814-a5c9-17de38545d08","year":null},"citing_paper":{"arxiv_id":"2508.20653","last_updated":"2025-08-28T10:57:13Z","snapshot_observed_at":"2026-08-14T21:36:25.585559Z","submitted_at":"2025-08-28T10:57:13Z","title":"Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V","version":1},"reference_index":21,"source":"pdf_text","source_observed_at":"2026-08-05T14:58:40.948978Z"},"links":{"citing_paper":"/paper/2508.20653"},"observation_digest":"sha256:c12499afb7df819df93149286b33b850115d7e02c758bd6eb66395c3ef1bf4f2","observation_id":"6823f6f5-d3ed-40c6-973d-12af2a7165f6","resolution":{"observed_at":"2026-08-05T14:58:41.731727Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T14:58:41.402478Z","title":"Mibench: A free, commercially represen- tative embedded benchmark suite,","venue":null,"work_id":"1ac633a9-c62e-4c5b-a3e5-eee4dacf810b","year":2001},"citing_paper":{"arxiv_id":"2508.20653","last_updated":"2025-08-28T10:57:13Z","snapshot_observed_at":"2026-08-14T21:36:25.585559Z","submitted_at":"2025-08-28T10:57:13Z","title":"Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V","version":1},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-05T14:58:41.137322Z"},"links":{"citing_paper":"/paper/2508.20653"},"observation_digest":"sha256:04866dbeeabf88384b3c932ab9e2fd9f71fdda35fac2eec287e6eefdc889548e","observation_id":"3762fa4d-da6e-4d5e-94ea-c7bb2ad1a63e","resolution":{"observed_at":"2026-08-05T14:58:41.509725Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T14:58:41.233278Z","title":"Cva6 v5.3.0,","venue":null,"work_id":"5b28ab87-1ef7-4613-ba34-a6ec2d42b908","year":null},"citing_paper":{"arxiv_id":"2508.20653","last_updated":"2025-08-28T10:57:13Z","snapshot_observed_at":"2026-08-14T21:36:25.585559Z","submitted_at":"2025-08-28T10:57:13Z","title":"Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V","version":1},"reference_index":23,"source":"pdf_text","source_observed_at":"2026-08-05T14:58:41.191226Z"},"links":{"citing_paper":"/paper/2508.20653"},"observation_digest":"sha256:90d8640e8ecb1a76f8ceefc7cf9dc994e990117a7ad2c72042bc1195a23e799c","observation_id":"564d1707-f229-4f96-a113-234a2529297d","resolution":{"observed_at":"2026-08-05T14:58:41.302806Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-22T06:32:14.747728+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"state":"measured"}}],"paper":{"arxiv_id":"2508.20653","last_updated":"2025-08-28T10:57:13Z","latest_version":1,"primary_category":"cs.AR","snapshot_observed_at":"2026-08-14T21:36:25.585559Z","submitted_at":"2025-08-28T10:57:13Z","title":"Microarchitecture Design and Benchmarking of Custom SHA-3 Instruction for RISC-V"},"reference_resolution":{"displayed":23,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":0,"verified_exact":0,"verified_fuzzy":23},"total_outbound_references":23},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"thesis":"As of 22 August 2026, this Paper Citation Record lists 23 of 23 outbound references and 0 inbound Pith citation observations for arXiv:2508.20653."}