{"as_of":"2026-08-07T22:14:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:3713991b6ffcde8dc91a3906da292941d1fa7087d926a5f8c0ab1f32cf8f2152","coverage":[{"denominator":25,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":25,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-04T20:43:15.537043Z","state":"measured"},{"denominator":25,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":25,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-07T06:34:17.273281+00:00","state":"measured"},{"denominator":0,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"cited_works","source_observed_at":null,"state":"measured"}],"external_citation_measurements":[],"inbound":[],"links":{"evidence":"/evidence","html":"/paper/2509.08416/citation-record","integrity":"/paper/2509.08416/integrity","json":"/paper/2509.08416/citation-record.json","paper":"/paper/2509.08416"},"outbound":[{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T20:43:12.855918Z","title":"On the robustness of code generation techniques: An empirical study on github copilot,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2509.08416","last_updated":"2025-09-10T09:00:32Z","snapshot_observed_at":"2026-08-07T20:47:47.496400Z","submitted_at":"2025-09-10T09:00:32Z","title":"AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-04T20:43:12.855918Z"},"links":{"citing_paper":"/paper/2509.08416"},"observation_digest":"sha256:5b403a7c2fd72052984a6b109a640a3bc3a987cf53d0a6f1fb41a75a4fa3ded9","observation_id":"d05f82ea-66c2-4746-89a6-65c24daa60ba","resolution":{"observed_at":"2026-08-04T20:43:12.855918Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2305.02309","last_updated":"2023-07-11T21:11:23Z","snapshot_observed_at":"2026-07-06T15:22:55.122322Z","submitted_at":"2023-05-03T17:55:25Z","title":"CodeGen2: Lessons for Training LLMs on Programming and Natural Languages","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2305.02309","snapshot_observed_at":"2026-08-04T20:43:12.940366Z","title":"Codegen2: Lessons for training llms on programming and natural languages,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2509.08416","last_updated":"2025-09-10T09:00:32Z","snapshot_observed_at":"2026-08-07T20:47:47.496400Z","submitted_at":"2025-09-10T09:00:32Z","title":"AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code","version":1},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-04T20:43:12.940366Z"},"links":{"cited_paper":"/paper/2305.02309","citing_paper":"/paper/2509.08416"},"observation_digest":"sha256:cd0d6f42e42e7d4f01ca11a6fbaf4941fce2a6c3519614d9059df87cddf124a3","observation_id":"b18a651e-8e80-4c51-8f7f-54cd1b9f41f2","resolution":{"observed_at":"2026-08-04T20:43:12.940366Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T20:43:17.312697Z","title":"Benchmarking large language models for automated verilog rtl code generation,","venue":null,"work_id":"2e6990a9-b861-4285-a99b-c1d73dfd123a","year":2023},"citing_paper":{"arxiv_id":"2509.08416","last_updated":"2025-09-10T09:00:32Z","snapshot_observed_at":"2026-08-07T20:47:47.496400Z","submitted_at":"2025-09-10T09:00:32Z","title":"AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code","version":1},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-04T20:43:13.006086Z"},"links":{"citing_paper":"/paper/2509.08416"},"observation_digest":"sha256:e146ee2deb5c3d373f720b9bd0184c692770f824a376af6b804dd8a5763f4b0c","observation_id":"337e701e-068f-4a0b-ac2f-93e57f87aa46","resolution":{"observed_at":"2026-08-04T20:43:17.317961Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2304.13840","last_updated":"2023-06-07T09:33:04Z","snapshot_observed_at":"2026-07-06T15:20:29.154658Z","submitted_at":"2023-04-26T21:56:03Z","title":"A Deep Learning Framework for Verilog Autocompletion Towards Design and Verification Automation","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2304.13840","snapshot_observed_at":"2026-08-04T20:43:13.097994Z","title":"A deep learning framework for verilog autocompletion towards design and verification automation,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2509.08416","last_updated":"2025-09-10T09:00:32Z","snapshot_observed_at":"2026-08-07T20:47:47.496400Z","submitted_at":"2025-09-10T09:00:32Z","title":"AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code","version":1},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-04T20:43:13.097994Z"},"links":{"cited_paper":"/paper/2304.13840","citing_paper":"/paper/2509.08416"},"observation_digest":"sha256:40e29a422ea6a10a20c5e598eb93875c214b2358704b915d815ec27a16ebae2f","observation_id":"a42ed1ab-3222-47a1-a07e-ef6f8639baf4","resolution":{"observed_at":"2026-08-04T20:43:13.097994Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T20:43:17.296117Z","title":"Openllm-rtl: Open dataset and benchmark for llm-aided design rtl generation(invited),","venue":null,"work_id":"01e4a2db-d0c9-4080-b5d6-fdb09064f39e","year":2024},"citing_paper":{"arxiv_id":"2509.08416","last_updated":"2025-09-10T09:00:32Z","snapshot_observed_at":"2026-08-07T20:47:47.496400Z","submitted_at":"2025-09-10T09:00:32Z","title":"AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code","version":1},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-08-04T20:43:13.172062Z"},"links":{"citing_paper":"/paper/2509.08416"},"observation_digest":"sha256:fecfed1c976592b8ff728073f29c59082de17046eae646042a376d4ac5510b63","observation_id":"ff5e74b4-38f6-4fb7-a555-9ce7e44f9524","resolution":{"observed_at":"2026-08-04T20:43:17.301351Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T20:43:13.271417Z","title":"Verilogeval: Evaluating large language models for verilog code generation,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2509.08416","last_updated":"2025-09-10T09:00:32Z","snapshot_observed_at":"2026-08-07T20:47:47.496400Z","submitted_at":"2025-09-10T09:00:32Z","title":"AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code","version":1},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-04T20:43:13.271417Z"},"links":{"citing_paper":"/paper/2509.08416"},"observation_digest":"sha256:8f683e2374c73fa0f90ed0b10c80fb704b312117964c91c6204203eeef23e491","observation_id":"61d475c9-4d1b-4de9-a9fa-b7495ded2cc0","resolution":{"observed_at":"2026-08-04T20:43:13.271417Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T20:43:17.269769Z","title":"Rtlcoder: Outperforming gpt-3.5 in design rtl generation with our open-source dataset and lightweight solution,","venue":null,"work_id":"231f9fe3-0a4d-4899-aa6b-916ac63e1317","year":2024},"citing_paper":{"arxiv_id":"2509.08416","last_updated":"2025-09-10T09:00:32Z","snapshot_observed_at":"2026-08-07T20:47:47.496400Z","submitted_at":"2025-09-10T09:00:32Z","title":"AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-04T20:43:13.358206Z"},"links":{"citing_paper":"/paper/2509.08416"},"observation_digest":"sha256:a17d2da9602cc5e36a0781bcc7463676121b00baefb5adf73f4c6e5aa28c6fc8","observation_id":"ec083c87-0660-4c5a-a67e-0da04ca7ae19","resolution":{"observed_at":"2026-08-04T20:43:17.274735Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2407.16237","last_updated":"2024-09-02T07:25:21Z","snapshot_observed_at":"2026-07-06T18:50:31.528338Z","submitted_at":"2024-07-23T07:22:25Z","title":"OriGen:Enhancing RTL Code Generation with Code-to-Code Augmentation and Self-Reflection","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2407.16237","snapshot_observed_at":"2026-08-04T20:43:13.447783Z","title":"Origen: Enhancing rtl code generation with code-to- code augmentation and self-reflection,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2509.08416","last_updated":"2025-09-10T09:00:32Z","snapshot_observed_at":"2026-08-07T20:47:47.496400Z","submitted_at":"2025-09-10T09:00:32Z","title":"AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code","version":1},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-04T20:43:13.447783Z"},"links":{"cited_paper":"/paper/2407.16237","citing_paper":"/paper/2509.08416"},"observation_digest":"sha256:4b30ac1a0344bbf3f4fa895ae220ad607eb50f867114b1494e7340613f38fba7","observation_id":"f770b0c3-672a-47a9-a917-7c635ec85a49","resolution":{"observed_at":"2026-08-04T20:43:13.447783Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2107.03374","last_updated":"2021-07-14T17:16:02Z","snapshot_observed_at":"2026-07-06T02:11:23.670680Z","submitted_at":"2021-07-07T17:41:24Z","title":"Evaluating Large Language Models Trained on Code","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2107.03374","snapshot_observed_at":"2026-08-04T20:43:13.568782Z","title":"Evaluating large language models trained on code,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2509.08416","last_updated":"2025-09-10T09:00:32Z","snapshot_observed_at":"2026-08-07T20:47:47.496400Z","submitted_at":"2025-09-10T09:00:32Z","title":"AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code","version":1},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-04T20:43:13.568782Z"},"links":{"cited_paper":"/paper/2107.03374","citing_paper":"/paper/2509.08416"},"observation_digest":"sha256:46a20bab1b59c9e5aa7237b030b3009622e6a96b7a76bbc5d84dfe7eacb3fe11","observation_id":"a2885405-6376-4d5e-92b7-bba5f3e98367","resolution":{"observed_at":"2026-08-04T20:43:13.568782Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.04887","last_updated":"2024-06-04T19:12:48Z","snapshot_observed_at":"2026-08-05T17:48:12.430235Z","submitted_at":"2023-11-08T18:46:39Z","title":"AutoChip: Automating HDL Generation Using LLM Feedback","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.04887","snapshot_observed_at":"2026-08-04T20:43:13.684192Z","title":"Autochip: Automating hdl generation using llm feedback,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2509.08416","last_updated":"2025-09-10T09:00:32Z","snapshot_observed_at":"2026-08-07T20:47:47.496400Z","submitted_at":"2025-09-10T09:00:32Z","title":"AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-04T20:43:13.684192Z"},"links":{"cited_paper":"/paper/2311.04887","citing_paper":"/paper/2509.08416"},"observation_digest":"sha256:149f86b72a4ff553ce5a0467e3327216ccc4396ff82099032ca1415a5e1ab225","observation_id":"81053871-d0f4-485d-94aa-d42267425767","resolution":{"observed_at":"2026-08-04T20:43:13.684192Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T20:43:13.793486Z","title":"Rtlfixer: Automatically fixing rtl syntax errors with large language model,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2509.08416","last_updated":"2025-09-10T09:00:32Z","snapshot_observed_at":"2026-08-07T20:47:47.496400Z","submitted_at":"2025-09-10T09:00:32Z","title":"AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code","version":1},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-04T20:43:13.793486Z"},"links":{"citing_paper":"/paper/2509.08416"},"observation_digest":"sha256:99932d917df96a9e1727917a999697cea6b30386dca5cce67f2cf5b9c087da9a","observation_id":"ba2e1215-8d73-4ce5-88c8-51f7f73c19c1","resolution":{"observed_at":"2026-08-04T20:43:13.793486Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2408.08927","last_updated":"2025-03-05T06:23:52Z","snapshot_observed_at":"2026-07-06T19:01:41.274385Z","submitted_at":"2024-08-15T20:06:06Z","title":"VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2408.08927","snapshot_observed_at":"2026-08-04T20:43:13.889616Z","title":"Verilogcoder: Autonomous verilog coding agents with graph-based planning and abstract syntax tree (ast)- based waveform tracing tool,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2509.08416","last_updated":"2025-09-10T09:00:32Z","snapshot_observed_at":"2026-08-07T20:47:47.496400Z","submitted_at":"2025-09-10T09:00:32Z","title":"AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code","version":1},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-04T20:43:13.889616Z"},"links":{"cited_paper":"/paper/2408.08927","citing_paper":"/paper/2509.08416"},"observation_digest":"sha256:4613288e7cece5647376eb5a144a65d595b0c296676b8a16c75c24e73caf2ce9","observation_id":"beb07df9-a0a9-413c-aaa0-debd7014c7b9","resolution":{"observed_at":"2026-08-04T20:43:13.889616Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T20:43:17.036447Z","title":"Myhdl: A python-based hardware description language,","venue":null,"work_id":"908c94bc-4946-4413-bd30-578b090b235c","year":2003},"citing_paper":{"arxiv_id":"2509.08416","last_updated":"2025-09-10T09:00:32Z","snapshot_observed_at":"2026-08-07T20:47:47.496400Z","submitted_at":"2025-09-10T09:00:32Z","title":"AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code","version":1},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-04T20:43:14.014000Z"},"links":{"citing_paper":"/paper/2509.08416"},"observation_digest":"sha256:50b44783576810c35ca2877513e803579499eefdd26711eee536b18eb60f221f","observation_id":"c009b431-ea1e-4a87-a9a2-a509ac58bf19","resolution":{"observed_at":"2026-08-04T20:43:17.142671Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T20:43:16.816091Z","title":"Exploiting computation reuse for stencil acceler- ators,","venue":null,"work_id":"936b6a65-4c8b-4d34-b10b-dc5809013029","year":2020},"citing_paper":{"arxiv_id":"2509.08416","last_updated":"2025-09-10T09:00:32Z","snapshot_observed_at":"2026-08-07T20:47:47.496400Z","submitted_at":"2025-09-10T09:00:32Z","title":"AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code","version":1},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-04T20:43:14.166429Z"},"links":{"citing_paper":"/paper/2509.08416"},"observation_digest":"sha256:76f67ad00b2d8f7049271709a6b007851406f840c944043995ab753c06d91651","observation_id":"8d9200e6-7a2c-4206-9556-3d8a80972feb","resolution":{"observed_at":"2026-08-04T20:43:16.919860Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2402.03375","last_updated":"2024-05-02T09:18:21Z","snapshot_observed_at":"2026-08-07T20:12:44.991572Z","submitted_at":"2024-02-03T08:00:12Z","title":"BetterV: Controlled Verilog Generation with Discriminative Guidance","version":3},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2402.03375","snapshot_observed_at":"2026-08-04T20:43:14.334778Z","title":"Betterv: Con- trolled verilog generation with discriminative guidance,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2509.08416","last_updated":"2025-09-10T09:00:32Z","snapshot_observed_at":"2026-08-07T20:47:47.496400Z","submitted_at":"2025-09-10T09:00:32Z","title":"AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code","version":1},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-08-04T20:43:14.334778Z"},"links":{"cited_paper":"/paper/2402.03375","citing_paper":"/paper/2509.08416"},"observation_digest":"sha256:d779d67aa1fb2ffdc62536ed7060a9d4bc8f9f067dc8637fcaa1f727f83c4ec5","observation_id":"c91e2155-1fd0-4cf1-8d63-646b441bab22","resolution":{"observed_at":"2026-08-04T20:43:14.334778Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T20:43:14.477090Z","title":"Verigen: A large language model for verilog code generation,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2509.08416","last_updated":"2025-09-10T09:00:32Z","snapshot_observed_at":"2026-08-07T20:47:47.496400Z","submitted_at":"2025-09-10T09:00:32Z","title":"AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code","version":1},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-04T20:43:14.477090Z"},"links":{"citing_paper":"/paper/2509.08416"},"observation_digest":"sha256:8e3a4be1a5aa433bf6df2ccc2200c523b588cc90e910047a550028335a5e275c","observation_id":"178ef397-ecb0-443f-aa56-ae5b3c09b8e5","resolution":{"observed_at":"2026-08-04T20:43:14.477090Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2203.13474","last_updated":"2023-02-27T21:26:48Z","snapshot_observed_at":"2026-07-06T12:52:16.992962Z","submitted_at":"2022-03-25T06:55:15Z","title":"CodeGen: An Open Large Language Model for Code with Multi-Turn Program Synthesis","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2203.13474","snapshot_observed_at":"2026-08-04T20:43:14.599727Z","title":"Codegen: An open large language model for code with multi-turn program synthesis,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2509.08416","last_updated":"2025-09-10T09:00:32Z","snapshot_observed_at":"2026-08-07T20:47:47.496400Z","submitted_at":"2025-09-10T09:00:32Z","title":"AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-04T20:43:14.599727Z"},"links":{"cited_paper":"/paper/2203.13474","citing_paper":"/paper/2509.08416"},"observation_digest":"sha256:9b01529a20fd5457647fe158b9d3edb020d9db6d2c1631113b7735617bab3e29","observation_id":"b71476eb-7adb-4eca-9d46-b8b4e4d32622","resolution":{"observed_at":"2026-08-04T20:43:14.599727Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T20:43:16.518799Z","title":"Gpt-3.5-turbo,","venue":null,"work_id":"fb0e58a2-2004-4eb5-8c88-0e00586e164c","year":2023},"citing_paper":{"arxiv_id":"2509.08416","last_updated":"2025-09-10T09:00:32Z","snapshot_observed_at":"2026-08-07T20:47:47.496400Z","submitted_at":"2025-09-10T09:00:32Z","title":"AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code","version":1},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-04T20:43:14.766041Z"},"links":{"citing_paper":"/paper/2509.08416"},"observation_digest":"sha256:a24fd18c2fa240fb32a4792412945b97a58b3fd8393bf9c6bf6ed4e79d12be63","observation_id":"8e04e80e-1817-4379-8a36-266ce86e7cc3","resolution":{"observed_at":"2026-08-04T20:43:16.627275Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T20:43:16.222055Z","title":"Gpt-4 technical report,","venue":null,"work_id":"44d52ac6-877d-4665-a899-c4efceaf2999","year":2023},"citing_paper":{"arxiv_id":"2509.08416","last_updated":"2025-09-10T09:00:32Z","snapshot_observed_at":"2026-08-07T20:47:47.496400Z","submitted_at":"2025-09-10T09:00:32Z","title":"AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code","version":1},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-08-04T20:43:14.934095Z"},"links":{"citing_paper":"/paper/2509.08416"},"observation_digest":"sha256:2df406b6b246a997d800a39781333c50fa642e40cbaeeaae808d2906c5ca1593","observation_id":"9b62a560-c9a9-49fe-a68e-1b159661ab73","resolution":{"observed_at":"2026-08-04T20:43:16.329709Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T20:43:15.047617Z","title":"Rtllm: An open-source benchmark for design rtl generation with large language model,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2509.08416","last_updated":"2025-09-10T09:00:32Z","snapshot_observed_at":"2026-08-07T20:47:47.496400Z","submitted_at":"2025-09-10T09:00:32Z","title":"AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code","version":1},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-08-04T20:43:15.047617Z"},"links":{"citing_paper":"/paper/2509.08416"},"observation_digest":"sha256:19e0cca02cd4d063faab5aae65d41b6909f3eca18278638e9dc1db2174864e0c","observation_id":"a1ed3f52-0ac1-499f-8d6e-1487f5a74620","resolution":{"observed_at":"2026-08-04T20:43:15.047617Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T20:43:15.973690Z","title":"A multi-expert large language model archi- tecture for verilog code generation,","venue":null,"work_id":"fd5780c3-d729-4619-bf94-c98fa92d69bd","year":2024},"citing_paper":{"arxiv_id":"2509.08416","last_updated":"2025-09-10T09:00:32Z","snapshot_observed_at":"2026-08-07T20:47:47.496400Z","submitted_at":"2025-09-10T09:00:32Z","title":"AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code","version":1},"reference_index":21,"source":"pdf_text","source_observed_at":"2026-08-04T20:43:15.206726Z"},"links":{"citing_paper":"/paper/2509.08416"},"observation_digest":"sha256:e16a18b19561a48a1051bb6245cc21987b5ad120c1d83678970097e31dc2c3c8","observation_id":"1080c7ad-84cd-42fe-827c-acce934cd4c5","resolution":{"observed_at":"2026-08-04T20:43:16.040097Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2308.12950","last_updated":"2024-01-31T19:47:26Z","snapshot_observed_at":"2026-07-06T16:10:07.931347Z","submitted_at":"2023-08-24T17:39:13Z","title":"Code Llama: Open Foundation Models for Code","version":3},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2308.12950","snapshot_observed_at":"2026-08-04T20:43:15.254197Z","title":"Code llama: Open foundation models for code,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2509.08416","last_updated":"2025-09-10T09:00:32Z","snapshot_observed_at":"2026-08-07T20:47:47.496400Z","submitted_at":"2025-09-10T09:00:32Z","title":"AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code","version":1},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-04T20:43:15.254197Z"},"links":{"cited_paper":"/paper/2308.12950","citing_paper":"/paper/2509.08416"},"observation_digest":"sha256:f6ce801745d49e70b6dea78905c568f076723acaac40fb883d50b0a63814da8f","observation_id":"ac223382-04e0-43a9-9621-67a493033bea","resolution":{"observed_at":"2026-08-04T20:43:15.254197Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2309.16609","last_updated":"2023-09-28T17:07:49Z","snapshot_observed_at":"2026-07-06T02:11:23.670680Z","submitted_at":"2023-09-28T17:07:49Z","title":"Qwen Technical Report","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2309.16609","snapshot_observed_at":"2026-08-04T20:43:15.308227Z","title":"Qwen technical report,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2509.08416","last_updated":"2025-09-10T09:00:32Z","snapshot_observed_at":"2026-08-07T20:47:47.496400Z","submitted_at":"2025-09-10T09:00:32Z","title":"AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code","version":1},"reference_index":23,"source":"pdf_text","source_observed_at":"2026-08-04T20:43:15.308227Z"},"links":{"cited_paper":"/paper/2309.16609","citing_paper":"/paper/2509.08416"},"observation_digest":"sha256:acb937ce02d82848b33783e9bf6c4446ba37adcfa87e5534c0b3d45fa8ad1952","observation_id":"f9e7f84b-2376-4795-86d2-908afff8719f","resolution":{"observed_at":"2026-08-04T20:43:15.308227Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2401.14196","last_updated":"2024-01-26T09:23:11Z","snapshot_observed_at":"2026-08-06T22:40:28.707813Z","submitted_at":"2024-01-25T14:17:53Z","title":"DeepSeek-Coder: When the Large Language Model Meets Programming -- The Rise of Code Intelligence","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2401.14196","snapshot_observed_at":"2026-08-04T20:43:15.416267Z","title":"Deepseek-coder: When the large language model meets programming–the rise of code intelligence,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2509.08416","last_updated":"2025-09-10T09:00:32Z","snapshot_observed_at":"2026-08-07T20:47:47.496400Z","submitted_at":"2025-09-10T09:00:32Z","title":"AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code","version":1},"reference_index":24,"source":"pdf_text","source_observed_at":"2026-08-04T20:43:15.416267Z"},"links":{"cited_paper":"/paper/2401.14196","citing_paper":"/paper/2509.08416"},"observation_digest":"sha256:c32558e9c1e5010cbd3bc923c05a17d2b0a5dc2b02f35d41dd850172bc4cab88","observation_id":"85dcc5e9-065b-4c48-8546-345d86232559","resolution":{"observed_at":"2026-08-04T20:43:15.416267Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T20:43:15.828713Z","title":"Introducing the next generation of claude,","venue":null,"work_id":"efa11dd8-c084-498d-933d-ff37bc6c7ce8","year":2024},"citing_paper":{"arxiv_id":"2509.08416","last_updated":"2025-09-10T09:00:32Z","snapshot_observed_at":"2026-08-07T20:47:47.496400Z","submitted_at":"2025-09-10T09:00:32Z","title":"AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code","version":1},"reference_index":25,"source":"pdf_text","source_observed_at":"2026-08-04T20:43:15.537043Z"},"links":{"citing_paper":"/paper/2509.08416"},"observation_digest":"sha256:b25769ee5ec7196c7655299b2185d39bc5aa011ccb052c7f608c9a6655a9d701","observation_id":"906c4bdf-6852-413d-b50e-fc3265afd0d2","resolution":{"observed_at":"2026-08-04T20:43:15.891949Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-07T06:34:17.273281+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"state":"measured"}}],"paper":{"arxiv_id":"2509.08416","last_updated":"2025-09-10T09:00:32Z","latest_version":1,"primary_category":"cs.AR","snapshot_observed_at":"2026-08-07T20:47:47.496400Z","submitted_at":"2025-09-10T09:00:32Z","title":"AutoVeriFix: Automatically Correcting Errors and Enhancing Functional Correctness in LLM-Generated Verilog Code"},"reference_resolution":{"displayed":25,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":16,"verified_exact":0,"verified_fuzzy":9},"total_outbound_references":25},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-07T06:34:17.273281+00:00","source":"crossref"},{"observed_at":"2026-08-07T06:34:11.927384+00:00","source":"retraction_watch"}],"thesis":"As of 7 August 2026, this Paper Citation Record lists 25 of 25 outbound references and 0 inbound Pith citation observations for arXiv:2509.08416."}