{"as_of":"2026-08-23T16:10:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:69dceea93716081b2aa06bc72be677b45d8c57efb039c25728ce0195287425ce","coverage":[{"denominator":49,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":49,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-04T10:21:50.012929Z","state":"measured"},{"denominator":49,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":49,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-23T06:30:58.430688+00:00","state":"measured"},{"denominator":0,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"cited_works","source_observed_at":null,"state":"measured"}],"external_citation_measurements":[],"inbound":[],"links":{"evidence":"/evidence","html":"/paper/2510.10676/citation-record","integrity":"/paper/2510.10676/integrity","json":"/paper/2510.10676/citation-record.json","paper":"/paper/2510.10676"},"outbound":[{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:46.052679Z","title":"Efficient Methods for Mapping Neural Machine Translator on FPGAs,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:46.052679Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:187940b61a1cf40dab0bd61bf2b050895a62e2a5d42ee97a9f234130fca34bfc","observation_id":"734ff16b-e8a4-4421-9095-4642953588fb","resolution":{"observed_at":"2026-08-04T10:21:46.052679Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:46.154827Z","title":"Algorithm-hardware Co-design of Attention Mechanism on FPGA Devices,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:46.154827Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:85bf1db33370f9ed28f7458767f0c4f9a0ef5006acf3f987caaacf7f5b56a8ab","observation_id":"c88d6f97-2f9f-4887-960a-686a42fb965e","resolution":{"observed_at":"2026-08-04T10:21:46.154827Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:46.225549Z","title":"A Survey of Multilingual Neural Machine Translation,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:46.225549Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:e4a28db2b710b28d07c1101c503dec2ced87cdc991c7eb286a363d6615c60747","observation_id":"d1e412a2-994e-40b3-b4cb-4b76deea6640","resolution":{"observed_at":"2026-08-04T10:21:46.225549Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:46.315079Z","title":"Natural Language Processing for Dialects of a Language: A Survey,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:46.315079Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:b2403d37a63e99a24aee5cebe6307f080df60f16e4546717959740d6b6d948d8","observation_id":"a20bc5d9-cf0c-4a05-a452-e3b47ef53489","resolution":{"observed_at":"2026-08-04T10:21:46.315079Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:46.401876Z","title":"SelfSeg: A Self-supervised Sub-word Segmentation Method for Neural Machine Translation,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:46.401876Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:22f0e293b8adce0c116469ab036c3af06d2b3a8c91b3f1d69c3932fe6b427c1d","observation_id":"d839f624-8406-4e9e-823c-2f810ebb4079","resolution":{"observed_at":"2026-08-04T10:21:46.401876Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:46.502894Z","title":"A Survey: Collaborative Hardware and Software Design in the Era of Large Language Models,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:46.502894Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:8582b04a3db5b1f5b1e0f3b71858b54ae62825aba16c32a506908a24745acb9d","observation_id":"e9f1b602-b27f-4346-b387-9672ff29549d","resolution":{"observed_at":"2026-08-04T10:21:46.502894Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:46.597626Z","title":"Indic-ST: A Large-Scale Multilingual Corpus for Low-Resource Speech-to-Text Translation,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:46.597626Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:a2abda176bfafc349ffb1abcb2ab249059f4ac9f7a1cdf6608faa89142d61c32","observation_id":"454fbce9-e248-4639-b439-44e659869383","resolution":{"observed_at":"2026-08-04T10:21:46.597626Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:46.678614Z","title":"OPU: An FPGA- Based Overlay Processor for Convolutional Neural Networks,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:46.678614Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:ba9b70aa9a5621197db36c9f18077dfc76ce9ab5985942780822ddc3bc604e09","observation_id":"de057ceb-e1f2-44f8-91bd-a5356b9edb65","resolution":{"observed_at":"2026-08-04T10:21:46.678614Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:46.737070Z","title":"An Energy-Efficient Reconfigurable LSTM Accelerator for Natural Language Processing,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:46.737070Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:1c94792dd78461cd0ab2be5d0136f25c74a4498d8883ba2190d9ee48aa435b24","observation_id":"59aa01ea-7cbc-4fa8-98e3-47ea01a4ece1","resolution":{"observed_at":"2026-08-04T10:21:46.737070Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2411.04699","last_updated":"2025-05-31T08:18:52Z","snapshot_observed_at":"2026-08-16T13:02:06.801566Z","submitted_at":"2024-11-07T13:33:34Z","title":"Towards Building Large Scale Datasets and State-of-the-Art Automatic Speech Translation Systems for 14 Indian Languages","version":3},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2411.04699","snapshot_observed_at":"2026-08-04T10:21:46.838830Z","title":"Bhasaanuvaad: A speech translation dataset for 13 indian languages,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:46.838830Z"},"links":{"cited_paper":"/paper/2411.04699","citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:44f379ba455b0649824e579c7cea4bb86ebbf17b61343c60ac832dae830f2304","observation_id":"88f89a3d-ea5d-4b6e-b078-184046adc31d","resolution":{"observed_at":"2026-08-04T10:21:46.838830Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:46.921724Z","title":"Towards building text-to-speech systems for the next billion users,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:46.921724Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:878488bf47375faf33a107441800088d21130dbc67ce4208f9deab1b4060dce4","observation_id":"c829cb4f-f31d-47a1-a187-21f9fb8250a0","resolution":{"observed_at":"2026-08-04T10:21:46.921724Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:46.985793Z","title":"Scaling neural machine translation to 200 languages,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:46.985793Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:ee3be56f769f5cad61593f7e5eb1d8338ef742bbeee9591e0b841c6fae6ad2ad","observation_id":"e520b929-68ea-41a6-9ffb-bfc9c1f78ce7","resolution":{"observed_at":"2026-08-04T10:21:46.985793Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:47.092301Z","title":"Robust speech recognition via large-scale weak super- vision,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:47.092301Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:ec932b7228520b3c2e8d24efbc090a5cd49cb68441136714a4d58c236a4b491e","observation_id":"7f33d887-5661-452b-bf0a-c4e592514158","resolution":{"observed_at":"2026-08-04T10:21:47.092301Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:47.161627Z","title":"ViTCoD: Vision Transformer Acceleration via Dedicated Algo- rithm and Accelerator Co-Design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:47.161627Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:4999b902eb44ffc09b5a6ff9ddc28e689b48e9f803b1c32df6f174d6b844534b","observation_id":"458671c0-8283-4425-9219-e8a5bfa07217","resolution":{"observed_at":"2026-08-04T10:21:47.161627Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:47.252449Z","title":"ViA: A Novel Vision-Transformer Accelerator Based on FPGA,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:47.252449Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:bde5115cf74b205e247769712db914acc87014143558b104390325a844d8d34e","observation_id":"a517b6d6-46d2-4904-b0e8-6d59516b4b53","resolution":{"observed_at":"2026-08-04T10:21:47.252449Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:47.318724Z","title":"EdgeBERT: Sentence-Level Energy Optimizations for Latency-Aware Multi-Task NLP Inference,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:47.318724Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:59f479242417a0bb7ab32a9c72de9f2f2e83cfb193b9a924dc65714585f17a1d","observation_id":"6c7ff8f7-6375-4b9e-95c8-674f99d62fb6","resolution":{"observed_at":"2026-08-04T10:21:47.318724Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:47.434923Z","title":"Hardware acceleration of fully quantized bert for efficient natural language processing,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:47.434923Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:28bd0402566aca0f136d979c1965624f792d53224ce1bcc874e3f26b5aad24ae","observation_id":"c5c2da49-4064-4ff5-8be1-263b50b673ac","resolution":{"observed_at":"2026-08-04T10:21:47.434923Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:47.619497Z","title":"AccelTran: A Sparsity-Aware Accelerator for Dy- namic Inference With Transformers,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:47.619497Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:9f7679e36d075afab77be9beba35af709eb22e4bf406ad42a13a2132f4a9d5a0","observation_id":"0f0851cf-ffed-459e-9b1e-e42ffa9a9b0d","resolution":{"observed_at":"2026-08-04T10:21:47.619497Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:47.870811Z","title":"A Fast and Flexible FPGA-based Accelerator for Natural Language Processing Neural Networks,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:47.870811Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:046527f6f07aa21c3e76174b7d5c8aaba3c5a3f1605646457f4ab826e97070c6","observation_id":"e501d3b8-6aa7-42cb-b540-f686880ae788","resolution":{"observed_at":"2026-08-04T10:21:47.870811Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:47.987454Z","title":"A 3: Accelerating Attention Mechanisms in Neural Networks with Approximation,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:47.987454Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:616f8e9ee46cd257560dce8b175c4c636c88ccd1a467b23745b8771f4aa6d5d9","observation_id":"f87213b5-845f-484f-b626-2a58c5e74d92","resolution":{"observed_at":"2026-08-04T10:21:47.987454Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:48.162161Z","title":"Uni-OPU: An FPGA- Based Uniform Accelerator for Convolutional and Transposed Convo- lutional Networks,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":21,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:48.162161Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:a66899d1da2ddf6069c7966e7288e983432d3f7789d67690bfc63e4b3a71ce67","observation_id":"49929172-89de-4fbf-a1e3-8c26c856a22e","resolution":{"observed_at":"2026-08-04T10:21:48.162161Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:48.340561Z","title":"HPTA: A High Performance Transformer Acceler- ator Based on FPGA,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:48.340561Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:c436c0bbeb934a51bbb88d822c34ff2cb61452e9f3b432b69f82bb48feda1712","observation_id":"98377cde-4e14-4c4b-adb4-e7c9615decf8","resolution":{"observed_at":"2026-08-04T10:21:48.340561Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:48.481559Z","title":"ELSA: hardware-software co-design for efficient, lightweight self-attention mechanism in neural networks,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":23,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:48.481559Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:b35ddedfaed34d163688300bf80b1478d118ce3ab220abc35c4a3b8af4cb8324","observation_id":"fe6e11c6-6ed3-455f-9516-a579f6600683","resolution":{"observed_at":"2026-08-04T10:21:48.481559Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:48.652792Z","title":"EdgeLLM: A Highly Efficient CPU- FPGA Heterogeneous Edge Accelerator for Large Language Models,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":24,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:48.652792Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:a1db5264b8b2ddab97a56033d4244c8232bc7e5926a2d2266d46ebcf248c984e","observation_id":"55be17e5-4002-43d5-81d8-3fd23186104d","resolution":{"observed_at":"2026-08-04T10:21:48.652792Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:48.859880Z","title":"A 16-nm SoC for Noise-Robust Speech and NLP Edge AI Inference With Bayesian Sound Source Separation and Attention-Based DNNs,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":25,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:48.859880Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:b0f90b2ca66348722974af5df20c1c40776698e2f7ea0c79836a42f93603d8b3","observation_id":"9a7e54de-5a81-41b6-adec-fe953132ab0f","resolution":{"observed_at":"2026-08-04T10:21:48.859880Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:49.076370Z","title":"A configurable cloud-scale DNN pro- cessor for real-time AI,","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":26,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:49.076370Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:c4f6022cf380b1e2b678d438de9eee2c4ebd7244244959b7dd5c8432aae5638a","observation_id":"01cc2679-6750-46e8-901c-b1d9dcf2e65a","resolution":{"observed_at":"2026-08-04T10:21:49.076370Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:49.280743Z","title":"Occamy: A 432-Core Dual-Chiplet Dual- HBM2E 768-DP-GFLOP/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":27,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:49.280743Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:eaa3f7f69e2d6d9eb08f0af0790162e7c51065a4fe183064daf2defa4ac225ee","observation_id":"29f43860-ddb2-409c-93c6-1fdcfab777e1","resolution":{"observed_at":"2026-08-04T10:21:49.280743Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:49.453622Z","title":"Maestro: A 302 GFLOPS/W and 19.8 GFLOPS RISC-V Vector-Tensor Architecture for Wearable Ultrasound Edge Computing,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":28,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:49.453622Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:a1aecefb73e4df789b381e8bf55b92f2e7899f5d9ba05b82457107210955ac73","observation_id":"8737c1f7-7d78-4f61-a997-bc6681bcc659","resolution":{"observed_at":"2026-08-04T10:21:49.453622Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:49.520973Z","title":"Parallel Accurate Minifloat MACCs for NN Inference on Versal FPGAs,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":29,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:49.520973Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:e45ab070a920bec5b89b9401491c2f48125ede42937ed74ba0059fc07c63782b","observation_id":"c8234a9b-a9c0-4695-89cf-ca0d5a2686eb","resolution":{"observed_at":"2026-08-04T10:21:49.520973Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:49.617602Z","title":"NVIDIA Blackwell Platform: Advancing Generative AI and Accelerated Computing,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":30,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:49.617602Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:d0f3a688fed9b394e65278ac1148324055c969042a3a68ba440afd62eecc9496","observation_id":"eb5ac4ef-83de-4e34-9dde-c13c7b463060","resolution":{"observed_at":"2026-08-04T10:21:49.617602Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:49.725403Z","title":"LPRE: Logarithmic Posit-enabled Reconfigurable edge-AI Engine,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":31,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:49.725403Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:b54e05ef581c2ac232104d633c750dd9b11c63f7541b0af3b8f384ae4b798ae3","observation_id":"2e9fab04-3334-4007-85d5-217ad4ad90f9","resolution":{"observed_at":"2026-08-04T10:21:49.725403Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:49.812963Z","title":"AMD XDNA NPU in Ryzen AI Processors,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":32,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:49.812963Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:81813d9335d92768ecde81bd00d76c9d9f889c1a017af5951fb6d5d07c95afdf","observation_id":"98649dce-c97e-477b-ad67-de7f233f6c2b","resolution":{"observed_at":"2026-08-04T10:21:49.812963Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:49.881914Z","title":"A Multi-Mode 8k-MAC HW-Utilization- Aware Neural Processing Unit With a Unified Multi-Precision Datapath in 4-nm Flagship Mobile SoC,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":33,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:49.881914Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:68cabf3855631048069d7b781903b07eac24968dde3c10df716d605e86c6a012","observation_id":"86405cba-78d5-4eda-91b2-13749563810f","resolution":{"observed_at":"2026-08-04T10:21:49.881914Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:49.922521Z","title":"A Low-Cost Floating-Point FMA Unit Supporting Package Operations for HPC-AI Applications,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":34,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:49.922521Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:3fd0ba7ea03a3c726f3da9485577c445ec9e7ac0cd07525710f83ef15b080676","observation_id":"69b367d0-e7e9-41c1-9db3-a4b63259a851","resolution":{"observed_at":"2026-08-04T10:21:49.922521Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:49.953542Z","title":"RaPiD: AI Accelerator for Ultra-low Precision Training and Inference,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":35,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:49.953542Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:f7a8b7611c2e40f2e2e0a8d7de9083cd9b3b9f99bb1b4c75fb36020f788fbb17","observation_id":"2be3a9ac-5965-45fa-84a9-5195d324705f","resolution":{"observed_at":"2026-08-04T10:21:49.953542Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2508.13049","last_updated":"2025-08-18T16:13:00Z","snapshot_observed_at":"2026-08-15T17:13:45.833368Z","submitted_at":"2025-08-18T16:13:00Z","title":"XR-NPE: High-Throughput Mixed-precision SIMD Neural Processing Engine for Extended Reality Perception Workloads","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2508.13049","snapshot_observed_at":"2026-08-04T10:21:49.958716Z","title":"XR-NPE: High-Throughput Mixed-precision SIMD Neural Processing Engine for Extended Reality Perception Workloads,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":36,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:49.958716Z"},"links":{"cited_paper":"/paper/2508.13049","citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:f0a309bca6c683bf67feea2898f198ba614187b73423bfb246c59bae2724ca9a","observation_id":"839f5ad1-41c2-42c9-8441-50e45cf69084","resolution":{"observed_at":"2026-08-04T10:21:49.958716Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:49.963681Z","title":"Exploring Hardware Ac- tivation Function Design: CORDIC Architecture in Diverse Floating Formats,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":37,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:49.963681Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:aef0f8d3a39086965040025ad3ac550fc25ecd76303b29b4cd8c47d8220a4432","observation_id":"0bf59857-f667-444d-96d9-243ba9ac88a6","resolution":{"observed_at":"2026-08-04T10:21:49.963681Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:49.967962Z","title":"Retrospective: A CORDIC Based Configurable Activation Function for NN Applications,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":38,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:49.967962Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:ee4b42c8f3654b1ff2091de230895aa14179b8aeb4011911200494cb9cb3cd39","observation_id":"aed9c2b9-a991-41d4-b141-2917197471b1","resolution":{"observed_at":"2026-08-04T10:21:49.967962Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:49.971854Z","title":"ASTRA: Reconfigurable Training Architecture Design for Nonlinear Softmax and Activation Functions in Transform- ers,","venue":null,"work_id":null,"year":2054},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":39,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:49.971854Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:91872323507b33e5faefd28b4d07d369aba62d2512b8e278bc1458cacbe7f558","observation_id":"8e401feb-8815-4e9c-80fc-24291bcbd74e","resolution":{"observed_at":"2026-08-04T10:21:49.971854Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:49.976148Z","title":"A Flexible Template for Edge Generative AI With High-Accuracy Accelerated Softmax and GELU,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":40,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:49.976148Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:325d75a2c2a134eec122eca10659c0a87b05c192cb7dbc10b06fde24f1ebe486","observation_id":"4bde0bd6-565a-4295-a770-24e9e6c280d0","resolution":{"observed_at":"2026-08-04T10:21:49.976148Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:49.979880Z","title":"Flex-PE: Flexible and SIMD Multiprecision Processing Element for AI Workloads,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":41,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:49.979880Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:f28ad7fa46f4c59627d57832b4ffd6dd8780674326363dff62c135f99befd7f4","observation_id":"81e98d69-e1fc-4908-94db-23197207604c","resolution":{"observed_at":"2026-08-04T10:21:49.979880Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:49.983714Z","title":"A Reconfigurable Processing Element for Multiple- Precision Floating/Fixed-Point HPC,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":42,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:49.983714Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:1d4b14253f7f499690613f82e5004dbce10bc085656b7c7729f8e77837c59db7","observation_id":"7f4a17c9-1611-4771-b449-7d47b05f812a","resolution":{"observed_at":"2026-08-04T10:21:49.983714Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:49.987835Z","title":"QuantMAC: Enhancing Hardware Performance in DNNs With Quantize Enabled Multiply-Accumulate Unit,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":43,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:49.987835Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:6cd69affa3ec28b89f2cff04b819b786718e512f71ed9cd0b5899eea5e2a5940","observation_id":"1e9f63d0-7500-4a77-b8dd-733adc20fea6","resolution":{"observed_at":"2026-08-04T10:21:49.987835Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:49.991721Z","title":"ReNPU: A Resource-efficient Multi-Mode Neural Processing Unit with Unified Multi-Precision Datapath for Mobile AI Workloads,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":44,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:49.991721Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:41b3f27749b29640b8c7ad8246d5acfb0117843fb79676c404da53ecae9b447d","observation_id":"56cb888d-e39a-412a-a21f-1eea1fc8e80c","resolution":{"observed_at":"2026-08-04T10:21:49.991721Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:49.996076Z","title":"ReAFM: A Reconfigurable Nonlinear Activation Function Module for Neural Networks,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":45,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:49.996076Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:86fd5b6e7f2b290d55ca24cc8065bd31b90eb3932be6ccd5ac2f7e6712d6adc5","observation_id":"8f1c05ee-b50e-49e1-8d36-d9e60d83e497","resolution":{"observed_at":"2026-08-04T10:21:49.996076Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:50.000062Z","title":"QForce- RL: Quantized FPGA-Optimized Reinforcement Learning Compute En- gine,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":46,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:50.000062Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:67c31261d1e95e019d1975353d1a9fd30a0bcaedb791e99878d0554daa6751db","observation_id":"b9023f3a-b5f8-420a-9144-cd5ef3deec80","resolution":{"observed_at":"2026-08-04T10:21:50.000062Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:50.004628Z","title":"Flex-SFU: Activation Func- tion Acceleration with Non-Uniform Piecewise Approximation,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":47,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:50.004628Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:030519ddbd3f055edd26c80db916e952597f3a82b5d9570fb92d6821d02dae13","observation_id":"0518197f-ea38-414a-8edf-1a817b583c73","resolution":{"observed_at":"2026-08-04T10:21:50.004628Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:50.008649Z","title":"TEA-S: A Tiny and Efficient Architecture for PLAC-Based Softmax in Transformers,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":48,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:50.008649Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:1f954a797cc4256d0e7b3faca2026a0d7ea9989c3ccab9c3380b92fc191be5c2","observation_id":"08690e32-0863-4763-b4f5-69cba0980618","resolution":{"observed_at":"2026-08-04T10:21:50.008649Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-04T10:21:50.012929Z","title":"ShortcutFusion: From Tensorflow to FPGA-Based Accelerator With a Reuse-Aware Memory Allocation for Shortcut Data,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation","version":1},"reference_index":49,"source":"pdf_text","source_observed_at":"2026-08-04T10:21:50.012929Z"},"links":{"citing_paper":"/paper/2510.10676"},"observation_digest":"sha256:0badecebed2b6d432cb573a4d29412e98750e3ba933f0a5f24848a547b064d86","observation_id":"adf87a18-66bb-4829-b65c-69c25ba6117f","resolution":{"observed_at":"2026-08-04T10:21:50.012929Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}}],"paper":{"arxiv_id":"2510.10676","last_updated":"2025-10-12T16:04:11Z","latest_version":1,"primary_category":"cs.AR","snapshot_observed_at":"2026-08-13T08:57:34.851423Z","submitted_at":"2025-10-12T16:04:11Z","title":"Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation"},"reference_resolution":{"displayed":49,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":49,"verified_exact":0,"verified_fuzzy":0},"total_outbound_references":49},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-23T06:30:58.430688+00:00","source":"crossref"},{"observed_at":"2026-08-23T06:30:53.778098+00:00","source":"retraction_watch"}],"thesis":"As of 23 August 2026, this Paper Citation Record lists 49 of 49 outbound references and 0 inbound Pith citation observations for arXiv:2510.10676."}