{"as_of":"2026-08-06T02:59:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:39b16730c2ed0cdf331b2abed28ec84afd6c130f6365cd158768753045649abd","coverage":[{"denominator":44,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":44,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-02T21:18:43.828011Z","state":"measured"},{"denominator":44,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":44,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-05T06:32:48.257954+00:00","state":"measured"},{"denominator":0,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"cited_works","source_observed_at":null,"state":"measured"}],"external_citation_measurements":[],"inbound":[],"links":{"evidence":"/evidence","html":"/paper/2602.20802/citation-record","integrity":"/paper/2602.20802/integrity","json":"/paper/2602.20802/citation-record.json","paper":"/paper/2602.20802"},"outbound":[{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:39.268718Z","title":"Faster and stronger: Unleashing data processing potential through hardware heterogeneity,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:39.268718Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:a6c84c2e81aae6625353c1614a21d67107b2ae0c7fd5f7f11ff8f618b802b8df","observation_id":"0ffceb1b-c8ba-466a-ab3e-1a94f290bbbb","resolution":{"observed_at":"2026-08-02T21:18:39.268718Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:39.380256Z","title":"June 2020 List,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:39.380256Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:c7fedbce57d7250810397a24793423ac8207d9dcdc3fb1212280aa7edf2183f0","observation_id":"fa3f4786-c5f8-4210-b1ac-4e5da8bc0922","resolution":{"observed_at":"2026-08-02T21:18:39.380256Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:39.517250Z","title":"June 2025 List,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:39.517250Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:8184257c2e8f293285d2271e74d3af006537b95bd3f7a4def90c9a3076d5c798","observation_id":"ca5a23eb-b297-4891-8aa0-8f98fb1187e6","resolution":{"observed_at":"2026-08-02T21:18:39.517250Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:39.641546Z","title":"Scalability analysis of avx-512 extensions,","venue":null,"work_id":null,"year":2082},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:39.641546Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:7de1cf43d01d6f8d2ece559e1899e53ec4a1df71b67230b983c62fed295713b3","observation_id":"9926ac15-237d-48ea-8441-e3bd51cf2cd5","resolution":{"observed_at":"2026-08-02T21:18:39.641546Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:39.731317Z","title":"An initial evaluation of arm’s scalable matrix extension,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:39.731317Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:f5f914043540be715f102bc2938073e2a29a08c5971e0f96daa82ace9db15bdf","observation_id":"0df0751b-0784-474a-a7fd-7ee7eb4b87c0","resolution":{"observed_at":"2026-08-02T21:18:39.731317Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:39.901935Z","title":"The world’s most valuable company just blew through an unprecedented milestone — CNN Business — edition.cnn.com,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:39.901935Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:ae97a80ced033676a6b796ee125c73367a9ea95b196af31ac80548a0f304fae3","observation_id":"bc6cb365-200e-4667-9e97-b3c4daf61b13","resolution":{"observed_at":"2026-08-02T21:18:39.901935Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:40.058210Z","title":"Breaking the valuation deadlock: Replacing the p/e ratio with the potential payback period (ppp) for loss-making companies-a case study on intel (2025),","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:40.058210Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:4c9a6346d91e26f7e1ae720d2dbd849d2202924d7539b4f2598ff75bce076f30","observation_id":"126f5bb9-da63-48e4-b380-a7e3c5aa1db4","resolution":{"observed_at":"2026-08-02T21:18:40.058210Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:40.137859Z","title":"Enabling Efficient GPU Communication over Multiple NICs with FuseLink,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:40.137859Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:d9d41fefb15f200dee7d49090896af4b4ab6caf1de0d758b768435592f3caeda","observation_id":"a1d53a2b-fea6-4bdd-9c1d-bd5551254b52","resolution":{"observed_at":"2026-08-02T21:18:40.137859Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:40.210338Z","title":"Bridging fpga and gpu over pcie: A low-latency communication path using avx- 512,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:40.210338Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:61256a95d434d119d71e515f098d750caa7e83e5a9c8d75e98efc4a3549277ea","observation_id":"813e33ac-6d66-4f6e-bdce-5c1fdc747094","resolution":{"observed_at":"2026-08-02T21:18:40.210338Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:40.262527Z","title":"Fast hbm access with fpgas: Analysis, architectures, and applications,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:40.262527Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:67f9719934103c5fe4c7a9cc12acd145eeb1d72b0a29acc626900af42bf86742","observation_id":"26ef18f6-fef5-4527-82ec-bca6b82782fa","resolution":{"observed_at":"2026-08-02T21:18:40.262527Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:40.327402Z","title":"Benchmarking and characterization of large language model inference on apple silicon,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:40.327402Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:e801cdfaa5e3651193d9c935c4c248fbc9ea29e8ee76c00c2d50a9b7a338f1fd","observation_id":"7bd5aa45-9a99-4595-8ee3-cdaf1a68dd9c","resolution":{"observed_at":"2026-08-02T21:18:40.327402Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:40.422955Z","title":"Performance analysis of gemm workloads on the amd versal platform,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:40.422955Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:132d9b505b2f828d7561ff105b39396852d7bfd145d74ba54278dd61f3b34e5d","observation_id":"75e3527b-2315-47eb-951c-2f6614cf7f4d","resolution":{"observed_at":"2026-08-02T21:18:40.422955Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:40.520944Z","title":"Stitching fpga fabrics with fabulous and openlane 2,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:40.520944Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:a3065a00d887797c38b2b74fa2d098139e4b9d247186d139c9e49914446fdb9a","observation_id":"db0c5b43-0c70-40c0-8ce7-e3abc59c99c6","resolution":{"observed_at":"2026-08-02T21:18:40.520944Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:40.644446Z","title":"Fpga-extended general purpose com- puter architecture,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:40.644446Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:70456cf093c62a65e75d7ea3f9b3bc70f69f764979adaeb42da514b916c717c5","observation_id":"5c0d417c-a176-4671-8de4-6668b7d93e0a","resolution":{"observed_at":"2026-08-02T21:18:40.644446Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:40.828960Z","title":"Versatile: Very fast partial reconfiguration controller,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:40.828960Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:46ed8c90b698ce310108634a84a4d2c908f267c5d984b6c80e6a89410c727a01","observation_id":"024c7df7-3f0c-4512-8df4-09ca1585121e","resolution":{"observed_at":"2026-08-02T21:18:40.828960Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:40.953873Z","title":"Looppoint: Checkpoint-driven sampled simulation for multi-threaded applications,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:40.953873Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:96e3694eab2fdbca10fa7ec460d7aaabda2922586a28f0806819d3a74d33b461","observation_id":"8448e306-0da6-4368-9db4-d7eda7a83165","resolution":{"observed_at":"2026-08-02T21:18:40.953873Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:41.047688Z","title":"Unexpected Diversity: Quantita- tive Memory Analysis for Zynq UltraScale+ Systems,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:41.047688Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:bd9956be41c5704184c8ea48663cacb637246d60f70d73ea48f25ec3719c2d5e","observation_id":"7c16c125-1bef-45e5-8da5-b0c59435999a","resolution":{"observed_at":"2026-08-02T21:18:41.047688Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:41.121007Z","title":"Using firesim to enable agile end-to-end risc-v computer architecture research,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:41.121007Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:8dfd65e3ddcc7ccd89caec875627d913b55ed6671e5241c8ceae51452d9ae831","observation_id":"3b780982-8b62-4611-877b-d1c14806f277","resolution":{"observed_at":"2026-08-02T21:18:41.121007Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:41.245730Z","title":"FlexBex: A RISC-V with a Reconfigurable Instruction Extension,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:41.245730Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:510477241a90af0f54fb75f19be9ed436380ca3d606bd1b2028639bde9bacb17","observation_id":"273cf05c-8df7-47bd-ac91-d2af32f442b7","resolution":{"observed_at":"2026-08-02T21:18:41.245730Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:41.335914Z","title":"FABulous: an Embedded FPGA Framework,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:41.335914Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:c90a8007ba2f55814e753bd8f82b74c43073faf72be12591161754ecd9219447","observation_id":"226d8716-b553-4a30-9da9-6efb88aa7a01","resolution":{"observed_at":"2026-08-02T21:18:41.335914Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:41.401425Z","title":"A soft dual-processor system with a partially run-time reconfigurable shared 128-bit simd engine,","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":21,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:41.401425Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:7d71ca047ed2909dffdc414e4e97d9cda8ee8e2a566ee3710f8d370227963bca","observation_id":"eb49c46b-2531-40a8-a4fb-021510aac995","resolution":{"observed_at":"2026-08-02T21:18:41.401425Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:41.575071Z","title":"Disc: The dynamic instruction set computer,","venue":null,"work_id":null,"year":1995},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:41.575071Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:b4cd7d6933db09f88157faa26791c5c36e0dcbde7143658dff18757608032292","observation_id":"71edc1a5-5b54-4b4e-b556-61a84ad7d1dc","resolution":{"observed_at":"2026-08-02T21:18:41.575071Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:41.700902Z","title":"Arnold: An efpga-augmented risc- v soc for flexible and low-power iot end nodes,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":23,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:41.700902Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:ea17690cc82c90bd1415d3b596372d7ba126173bdf43dc53e945b0d7a12f2d58","observation_id":"5f415513-ba2b-4912-9171-6ca5cd405e56","resolution":{"observed_at":"2026-08-02T21:18:41.700902Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:41.840292Z","title":"efpgas: Architectural explorations, system integration & a visionary industrial survey of programmable technologies,","venue":null,"work_id":null,"year":2011},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":24,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:41.840292Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:2a0d3c4ce421cc2e77dcb0e15a41eb37a7903b54aa4595d19a94de32f7e2b1fc","observation_id":"bdf65cdd-a06a-48f3-8d9e-2f1d4a398320","resolution":{"observed_at":"2026-08-02T21:18:41.840292Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:41.910581Z","title":"The road not taken: efpga accelerators utilized for soc security auditing,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":25,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:41.910581Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:7c4798362d16273661708afd1e8637ddda91c96d182537f1c5aecbfe1a9c2005","observation_id":"83124f21-55ca-431b-8ba4-da63f3f3bc0b","resolution":{"observed_at":"2026-08-02T21:18:41.910581Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:42.003281Z","title":"Rispp: A run-time adaptive reconfigurable embedded processor,","venue":null,"work_id":null,"year":2009},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":26,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:42.003281Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:0dcd4cc9160abfdaf137143876e33ca55ab7da6e86a04cddf43d0fd350e3d3b4","observation_id":"68c11ee2-31d5-45a7-adbc-c79c7d4b7f39","resolution":{"observed_at":"2026-08-02T21:18:42.003281Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:42.085838Z","title":"efpga redaction,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":27,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:42.085838Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:1b7e895a7a7ed52d31167f9c1e0ee82b63f6e8973cd8366563b459999c2b84df","observation_id":"9df57042-3109-4404-b3f4-21dc82c34c9f","resolution":{"observed_at":"2026-08-02T21:18:42.085838Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:42.194526Z","title":"Fpga dynamic and partial reconfiguration: A survey of architectures, methods, and applications,","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":28,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:42.194526Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:7408ab4c35fe9aeb0b3b8baef6bfe6c352966eddf5b73fdb93096ac888533427","observation_id":"6332cf74-d825-4970-81f4-13fa1ffe0058","resolution":{"observed_at":"2026-08-02T21:18:42.194526Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:42.326403Z","title":"Fos: A modular fpga operating system for dynamic workloads,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":29,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:42.326403Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:e3d5519f450d24f3c5a10256697fb502dda40c92b8fb9130a716e4fc3412e12f","observation_id":"bdf758bb-68c6-4e7f-8d5a-313a1c6fad35","resolution":{"observed_at":"2026-08-02T21:18:42.326403Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:42.489731Z","title":"AXI HWICAP v3.0 Product Guide (PG134),","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":30,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:42.489731Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:7a0e4465872139c570981237a15f05f0e4f06e7909f13253503798a4e17a2193","observation_id":"731be1e7-66b2-44e5-897a-c99510f63902","resolution":{"observed_at":"2026-08-02T21:18:42.489731Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:42.554005Z","title":"Intel intrinsics guide,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":31,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:42.554005Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:c1320b00de4a6b67d5169398fea1e7ca223cc0ed2d9114fecbe20b16bed71b5d","observation_id":"be5da109-0d41-4593-87b5-f75b6374d93f","resolution":{"observed_at":"2026-08-02T21:18:42.554005Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:42.682687Z","title":"Zuma: An open fpga overlay ar- chitecture,","venue":null,"work_id":null,"year":2012},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":32,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:42.682687Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:a4a4b8b8569590f3f70f784c70b967580d4248aa00bb3deba662a910ab094a5c","observation_id":"a381610b-ddfd-49f5-ac3c-06a456468e37","resolution":{"observed_at":"2026-08-02T21:18:42.682687Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:42.747232Z","title":"Embedding fpga overlays into configurable systems-on-chip: Reconos meets zuma,","venue":null,"work_id":null,"year":2014},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":33,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:42.747232Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:b72ecc31a32bff1bbf00007550293e6d17fba88d2bc2438f713fd9bed4d134e7","observation_id":"fc4b1131-3e8a-4e8f-998f-969ca6452bd1","resolution":{"observed_at":"2026-08-02T21:18:42.747232Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:42.806653Z","title":"A survey of design and optimization for systolic array-based dnn accelerators,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":34,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:42.806653Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:eeac26e6056d2e951b9a731d122453b77ba46a2aea1da833d6e186a961296947","observation_id":"2a2f286b-2a0f-428d-95ac-226c57c8ee8a","resolution":{"observed_at":"2026-08-02T21:18:42.806653Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:42.937514Z","title":"GitHub - htfab/rotfpga2,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":35,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:42.937514Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:606f3f5be6a8ee72a4b8daf604d65014ab763cdc1321c61b71824e8ed85f1f77","observation_id":"0467ccc3-339f-44f8-ad54-a97539ffc465","resolution":{"observed_at":"2026-08-02T21:18:42.937514Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:43.061888Z","title":"Overgen: Improving fpga usability through domain-specific overlay generation,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":36,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:43.061888Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:0126dbb8ebd423be4ad25f55636e1b1d7dca590b5c40d7e6d536cfed6f084e2b","observation_id":"e149b54f-0015-4cf6-afe4-288511173e85","resolution":{"observed_at":"2026-08-02T21:18:43.061888Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:43.191945Z","title":"Comparing fpga vs. custom cmos and the impact on processor microarchitecture,","venue":null,"work_id":null,"year":2011},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":37,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:43.191945Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:dcfaa762260dcd25f80741f3fd155f95fb791eadb684fd52a5892720ec00c1cb","observation_id":"541a7a28-d490-4f90-a5f6-3d1092cf85d7","resolution":{"observed_at":"2026-08-02T21:18:43.191945Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:43.307512Z","title":"Simodense: a RISC- V softcore optimised for exploring custom SIMD instructions,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":38,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:43.307512Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:b566b47208815d39df695611d969cb181d3d8b360d8874499c23fb9048e78221","observation_id":"30759c52-7b79-44af-b8c3-403a76c2bfc4","resolution":{"observed_at":"2026-08-02T21:18:43.307512Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:43.380749Z","title":"Vtr 9: Open-source cad for fabric and beyond fpga architecture exploration,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":39,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:43.380749Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:1db007bb0dc25066865285f480e33d82deb39c74b200c5ffed99389dacb1c59f","observation_id":"9c8b941e-5b12-4665-a226-9b601c02106e","resolution":{"observed_at":"2026-08-02T21:18:43.380749Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:43.491567Z","title":"Making a case for an arm cortex-a9 cpu interlay replacing the neon simd unit,","venue":null,"work_id":null,"year":2017},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":40,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:43.491567Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:454e610e41271cbb7cad1bc9ef274ce05db075a17c31e48c3fd4b6dc53b94c79","observation_id":"f38ee6fe-a9b7-4c35-8a36-27e3450a0721","resolution":{"observed_at":"2026-08-02T21:18:43.491567Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:43.552805Z","title":"Stream: Sustainable memory bandwidth in high performance computers,","venue":null,"work_id":null,"year":1991},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":41,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:43.552805Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:fbd9bf3cae7acecee73918144dc9cc53ea59be96095ccc4c82b4be764957f881","observation_id":"6bee412d-c9e4-44ed-9eda-d37491884ca1","resolution":{"observed_at":"2026-08-02T21:18:43.552805Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:43.635138Z","title":"Building openlane: A 130nm openroad- based tapeout- proven flow : Invited paper,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":42,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:43.635138Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:fcecd38082486473184f791a35c00005cc7c58872d39663e4c9b263135f9db51","observation_id":"09b0adc1-d1f5-4924-9c4e-4b911f76be95","resolution":{"observed_at":"2026-08-02T21:18:43.635138Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:43.761937Z","title":"Asap7: A 7-nm finfet predictive process design kit,","venue":null,"work_id":null,"year":2016},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":43,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:43.761937Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:04ae5e63e549cbac9259798cd166a0bda0050633130da841b0aef60e678f8e84","observation_id":"6a25f0c2-2b63-4d08-b3c3-3cae0efefd89","resolution":{"observed_at":"2026-08-02T21:18:43.761937Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T21:18:43.828011Z","title":"A distributed approach to silicon compilation: Invited,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions","version":3},"reference_index":44,"source":"pdf_text","source_observed_at":"2026-08-02T21:18:43.828011Z"},"links":{"citing_paper":"/paper/2602.20802"},"observation_digest":"sha256:dd071b0625db51116ce46f4c1a3bed33e0a86fd373d61c91cd4ec11f2241b555","observation_id":"0ca1408d-63cb-4572-9830-1b111cf0bfd7","resolution":{"observed_at":"2026-08-02T21:18:43.828011Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}}],"paper":{"arxiv_id":"2602.20802","last_updated":"2026-06-29T11:01:27Z","latest_version":3,"primary_category":"cs.AR","snapshot_observed_at":"2026-08-02T21:18:38.499458Z","submitted_at":"2026-02-24T11:43:34Z","title":"LUTstructions: Self-loading FPGA-based Reconfigurable Instructions"},"reference_resolution":{"displayed":44,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":44,"verified_exact":0,"verified_fuzzy":0},"total_outbound_references":44},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-05T06:32:48.257954+00:00","source":"crossref"},{"observed_at":"2026-08-05T06:32:44.755628+00:00","source":"retraction_watch"}],"thesis":"As of 6 August 2026, this Paper Citation Record lists 44 of 44 outbound references and 0 inbound Pith citation observations for arXiv:2602.20802."}