Cooling Channel Design Optimization for High Power Multi-chip Packages

Michael Acquah; Zheng Liu

arxiv: 2605.20657 · v1 · pith:3I7WFTATnew · submitted 2026-05-20 · 📡 eess.SY · cs.SY· stat.AP

Cooling Channel Design Optimization for High Power Multi-chip Packages

Michael Acquah , Zheng Liu This is my paper

Pith reviewed 2026-05-21 04:13 UTC · model grok-4.3

classification 📡 eess.SY cs.SYstat.AP

keywords cooling channel optimizationmulti-chip packagesthermal managementinterdigitated coolingsurrogate-based optimizationhigh-performance computingGPU thermal designembedded microchannels

0 comments

The pith

A surrogate-optimized interdigitated cooling design cuts peak chip temperatures by 140.45°C in high-power multi-chip packages.

A machine-rendered reading of the paper's core claim, the machinery that carries it, and where it could break.

The paper develops a physics-based framework that models steady-state heat conduction and coolant flow through parameterized interdigitated channels in multi-chip modules. It uses a surrogate approximation of the temperature response to geometric variables, then applies mixed-integer quadratic programming to minimize a weighted combination of peak and average chip temperatures while enforcing extra cooling near high-load GPU regions. The framework is demonstrated on a two-GPU one-CPU configuration representative of the NVIDIA GB200. A sympathetic reader would care because such temperature drops directly address the primary barrier to scaling performance and power density in next-generation heterogeneous packages without enlarging the module or increasing coolant flow rates.

Core claim

The authors parameterize an interdigitated cooling architecture with variables for channel count, width, and regional expansion, couple a porous-media flow model with row-wise energy balance to predict chip temperatures, and optimize the layout via a surrogate-assisted mixed-integer quadratic program. When applied to a representative GB200-style multi-chip package, the resulting design lowers peak chip temperature by 140.45°C and average chip temperature by 35.87°C relative to the baseline configuration.

What carries the argument

Interdigitated cooling architecture parameterized by channel count, width, and expansion over chip regions, approximated by a surrogate model and optimized with mixed-integer quadratic programming under GPU-coverage constraints.

If this is right

The same parameterization and optimization procedure can be reused for other heterogeneous multi-chip layouts with different power distributions.
Adding more weight to the GPU regions in the objective forces cooling channels to concentrate where thermal loads are highest.
The surrogate-plus-MIQP approach replaces exhaustive high-fidelity simulations for each candidate geometry, making systematic layout exploration tractable.

Where Pith is reading between the lines

These are editorial extensions of the paper, not claims the author makes directly.

If the surrogate remains accurate at higher power densities, the framework could guide cooling designs for future chips beyond the GB200 power envelope.
The method's reliance on a porous-media approximation suggests a natural next test: comparing predicted flow resistance against full Navier-Stokes simulations or experimental pressure-drop data.
Because the optimization is purely geometric, the same machinery could later incorporate manufacturing constraints such as minimum feature size or etch tolerances.

Load-bearing premise

The surrogate model accurately reproduces the relationship between the geometric channel parameters and the resulting chip temperature fields.

What would settle it

Build a physical prototype of the reported optimal channel geometry, apply the same power map, and measure the steady-state peak temperature; a value more than 20°C higher than the predicted optimum would falsify the optimization result.

Figures

Figures reproduced from arXiv: 2605.20657 by Michael Acquah, Zheng Liu.

**Figure 2.** Figure 2: FIGURE 2: Definition of the geometric design variables for the cooling manifold. [PITH_FULL_IMAGE:figures/full_fig_p004_2.png] view at source ↗

**Figure 3.** Figure 3: FIGURE 3: (a) Schematic representation of the reduced-order ther [PITH_FULL_IMAGE:figures/full_fig_p004_3.png] view at source ↗

**Figure 4.** Figure 4: FIGURE 4: Comparison between the baseline manifold-fed configuration (a) and the optimized cooling-channel layout; (b) The optimized [PITH_FULL_IMAGE:figures/full_fig_p005_4.png] view at source ↗

**Figure 5.** Figure 5: FIGURE 5: Temperature contour field for the optimized cooling [PITH_FULL_IMAGE:figures/full_fig_p006_5.png] view at source ↗

**Figure 6.** Figure 6: FIGURE 6: Temperature contour comparison between the baseline configuration (a) and the optimized configuration (b). The optimized [PITH_FULL_IMAGE:figures/full_fig_p007_6.png] view at source ↗

**Figure 7.** Figure 7: FIGURE 7: Comparison of representative cooling-channel configurations showing (a) maximum chip temperature, (b) average chip temper [PITH_FULL_IMAGE:figures/full_fig_p008_7.png] view at source ↗

**Figure 8.** Figure 8: FIGURE 8: Coolant temperature evolution along the flow direction [PITH_FULL_IMAGE:figures/full_fig_p008_8.png] view at source ↗

read the original abstract

Thermal management is a major challenge in next-generation high-performance computing systems, particularly for heterogeneous multi-chip packages such as the NVIDIA GB200 Grace Blackwell Superchip. In this work, a physics-based computational framework is developed to optimize embedded cooling channel layouts for high-power multi-chip modules. The model couples steady-state heat conduction with a porous media-based representation of coolant transport, coupled with a row-wise coolant energy balance, to estimate chip temperature fields within microchannel networks. Unlike conventional designs, an interdigitated cooling architecture is parameterized using geometric variables, including channel count, width, and expansion over chip regions, enabling systematic design exploration. To enable efficient optimization, a surrogate-based approach is employed to approximate the relationship between geometric parameters and temperature metrics. The resulting model is optimized using a mixed-integer quadratic programming algorithm to minimize a weighted objective based on peak and average chip temperatures. To improve physical relevance, channel placement is further constrained to increase cooling coverage near GPU regions, where thermal loads are highest. The framework is applied to a representative multi-chip configuration based on NVIDIA GB200 architecture, consisting of two graphics processing units and one central processing unit. The results demonstrate that the optimal design reduces the peak chip temperature by 140.45{\deg}C and the average chip temperature by 35.87{\deg}C compared to the baseline configuration.

Editorial analysis

A structured set of objections, weighed in public.

Desk editor's note, referee report, simulated authors' rebuttal, and a circularity audit. Tearing a paper down is the easy half of reading it; the pith above is the substance, this is the friction.

Desk Editor's Note private letter to a colleague

The optimization framework is a reasonable engineering extension but the huge claimed temperature drops rest on an unvalidated surrogate, so the numbers need checking before they can be trusted.

read the letter

The main takeaway is that this paper sets up a parameterized interdigitated microchannel model for a GB200-like package, runs it through a surrogate, and feeds the result into mixed-integer quadratic programming to cut peak and average chip temperatures. The reported drops are 140 °C peak and 36 °C average versus baseline, which would be useful if they hold up. The modeling couples steady conduction with porous-media flow and a row-wise energy balance, then adds geometric variables for channel count, width, and expansion plus a constraint to favor GPU regions. That part is straightforward and fits the problem of heterogeneous high-power modules. The parameterization and the focus on real hardware loads are the parts that could actually help someone designing similar systems. The soft spot is exactly where the stress-test note points: the surrogate. With only two geometric parameters the model is cheap to sample, yet the abstract gives no leave-one-out error, no hold-out residuals against the full physics solver, and no re-run of the porous-media equations at the reported optimum. Any local bias in the surrogate near the high-flux GPU zones gets handed straight to the optimizer and can produce inflated deltas. The baseline itself is also not spelled out in enough detail to judge how fair the comparison is. This is aimed at thermal engineers working on HPC and AI packaging who already use CFD or reduced-order models and want a template for channel layout exploration. A reader could borrow the parameterization or the constraint approach even if they rebuild the numerics themselves. The work is coherent on its own terms and shows honest engagement with the engineering constraints, so it deserves a serious referee rather than a desk reject. A review would mainly ask for surrogate accuracy metrics and a direct physics check at the optimum point, after which the quantitative claims could be assessed properly.

Referee Report

3 major / 2 minor

Summary. The paper develops a physics-based computational framework coupling steady-state heat conduction with a porous-media representation of coolant flow and row-wise energy balance to model temperature fields in interdigitated microchannel networks for high-power multi-chip packages such as the NVIDIA GB200 Grace Blackwell Superchip. Geometric parameters (channel count, width, and expansion) are optimized via a surrogate model and mixed-integer quadratic programming to minimize a weighted combination of peak and average chip temperatures, subject to constraints favoring GPU cooling coverage. The central quantitative claim is that the resulting optimal design reduces peak chip temperature by 140.45 °C and average chip temperature by 35.87 °C relative to a baseline configuration.

Significance. If the surrogate accurately captures the underlying physics and the reported optima are verified by direct model re-evaluation, the work would supply a practical, parameterized design tool for embedded cooling in heterogeneous HPC modules, addressing a timely thermal-management bottleneck. The explicit incorporation of GPU-region constraints and the use of MIQP for discrete channel decisions are methodologically sound strengths that could translate to other multi-chip layouts.

major comments (3)

[Surrogate Model] Surrogate Model section (inferred from abstract description of surrogate-based approach): no leave-one-out error, maximum residual on hold-out CFD/physics-model points, or any other quantitative fidelity metric is reported for the surrogate that maps the two geometric parameters to peak/average temperatures. Because the headline deltas (140.45 °C peak, 35.87 °C average) are produced by feeding this surrogate into MIQP, any local bias near high-flux GPU regions would be directly inherited and amplified by the optimizer.
[Results] Results section (abstract and optimization-results paragraph): the claimed temperature reductions are not accompanied by re-evaluation of the full physics model (porous-media flow + row-wise energy balance + conduction) at the reported optimal geometry, nor by any experimental comparison or mesh-convergence study. Without this verification step, the quantitative outcomes rest on an untested approximation and cannot be considered load-bearing evidence for the central claim.
[Model Formulation] Model Formulation section: the porous-media permeability and effective conductivity parameters are introduced without stated calibration procedure, sensitivity analysis, or comparison against detailed CFD or experimental data for the specific channel geometries. These parameters directly determine the temperature fields that enter the objective, so their justification is essential for trusting the optimization outcomes.

minor comments (2)

[Abstract] The abstract states the number of geometric design variables but does not indicate how many discrete channel configurations were evaluated to build the surrogate; adding this detail would clarify computational cost.
[Model Formulation] Notation for the row-wise energy balance and the weighting factors in the objective function should be introduced with explicit symbols and units in the main text for reproducibility.

Simulated Author's Rebuttal

3 responses · 0 unresolved

We thank the referee for the constructive and detailed comments. We address each major comment point by point below, indicating the revisions we will make to strengthen the manuscript's rigor and transparency.

read point-by-point responses

Referee: [Surrogate Model] no leave-one-out error, maximum residual on hold-out CFD/physics-model points, or any other quantitative fidelity metric is reported for the surrogate that maps the two geometric parameters to peak/average temperatures. Because the headline deltas (140.45 °C peak, 35.87 °C average) are produced by feeding this surrogate into MIQP, any local bias near high-flux GPU regions would be directly inherited and amplified by the optimizer.

Authors: We agree that quantitative fidelity metrics for the surrogate are essential to support the optimization results. The surrogate was trained on evaluations from the physics-based model, but these error metrics were not reported in the original manuscript. In the revision we will add a dedicated subsection to the Surrogate Model section that reports leave-one-out cross-validation errors, maximum residuals on an independent hold-out set of physics-model points, and R-squared values, with explicit discussion of accuracy in high-flux GPU regions. revision: yes
Referee: [Results] the claimed temperature reductions are not accompanied by re-evaluation of the full physics model (porous-media flow + row-wise energy balance + conduction) at the reported optimal geometry, nor by any experimental comparison or mesh-convergence study. Without this verification step, the quantitative outcomes rest on an untested approximation and cannot be considered load-bearing evidence for the central claim.

Authors: We acknowledge that direct verification of the optimal geometry with the full physics model is required. We will re-evaluate the complete model (porous-media flow, row-wise energy balance, and conduction) at the reported optimum and include these results in the revised Results section to confirm the surrogate predictions. A mesh-convergence study will also be added. Experimental comparison is outside the scope of this computational framework and will be noted as future work. revision: partial
Referee: [Model Formulation] the porous-media permeability and effective conductivity parameters are introduced without stated calibration procedure, sensitivity analysis, or comparison against detailed CFD or experimental data for the specific channel geometries. These parameters directly determine the temperature fields that enter the objective, so their justification is essential for trusting the optimization outcomes.

Authors: The permeability and effective conductivity were selected from established literature correlations for microchannel geometries with similar hydraulic diameters and flow conditions. We agree that explicit justification is needed. In the revised Model Formulation section we will add the parameter selection rationale, a sensitivity analysis for ±10% and ±20% variations, and comparisons against a subset of detailed CFD simulations for representative channel geometries. revision: yes

Circularity Check

0 steps flagged

No circularity: physics-based model optimized via surrogate and MIQP

full rationale

The paper constructs a physics-based thermal model (steady-state conduction + porous-media coolant transport + row-wise energy balance), parameterizes an interdigitated channel layout with geometric variables, evaluates the model to train a surrogate, and applies external MIQP to minimize a weighted peak/average temperature objective under placement constraints. The reported deltas (140.45 °C peak, 35.87 °C average) are differences between the optimized design and baseline as produced by this pipeline. No equation reduces the output temperatures to a fitted parameter by construction, no self-citation is load-bearing for the central result, and the surrogate serves only as an efficiency tool rather than redefining the physics. The derivation remains self-contained against the stated physical assumptions and external optimization algorithm.

Axiom & Free-Parameter Ledger

2 free parameters · 2 axioms · 0 invented entities

Only the abstract is available, so the ledger is inferred from the high-level description of the model and optimization; full details on parameters and assumptions are absent.

free parameters (2)

Objective function weights
Weights balancing peak versus average temperature in the minimization objective.
Geometric design variables
Channel count, width, and expansion parameters used to define the interdigitated layout.

axioms (2)

domain assumption Porous media representation accurately models coolant transport and heat transfer in microchannel networks
Invoked to couple with steady-state heat conduction for estimating chip temperature fields.
domain assumption Steady-state conditions govern the chip temperature fields
Basis for the physics-based computational framework.

pith-pipeline@v0.9.0 · 5766 in / 1389 out tokens · 62274 ms · 2026-05-21T04:13:56.343872+00:00 · methodology

discussion (0)

Reference graph

Works this paper leans on

20 extracted references · 20 canonical work pages · 1 internal anchor

[1]

High- performanceheatsinkingforVLSI

Tuckerman, David B and Pease, Roger Fabian W. “High- performanceheatsinkingforVLSI.”IEEEElectrondevice lettersVol. 2 No. 5 (2005): pp. 126–129

work page 2005
[2]

High efficiency liquid cooling system of power electronic converter

Liang, Jinhua, Xu, Haiping, Yuan, Zengquan and Zhou, Peng. “High efficiency liquid cooling system of power electronic converter.”2020 5th Asia Conference on Power 8 Copyright©2026 by ASME andElectricalEngineering(ACPEE):pp.1270–1275.2020. IEEE

work page arXiv 2020
[3]

Assessment of high-heat-flux thermal management schemes

Mudawar, Issam. “Assessment of high-heat-flux thermal management schemes.”IEEE transactions on components andpackagingtechnologiesVol.24No.2(2002): pp.122– 141

work page 2002
[4]

Machine learn- ing aided design and optimization of thermal metamateri- als

Zhu, Changliang, Bamidele, Emmanuel Anuoluwa, Shen, Xiangying, Zhu, Guimei and Li, Baowen. “Machine learn- ing aided design and optimization of thermal metamateri- als.”Chemical ReviewsVol. 124 No. 7 (2024): pp. 4258– 4331

work page 2024
[5]

Thermal and power challenges inhighperformancecomputingsystems

Natarajan, Venkat, Deshpande, Anand, Solanki, Sudarshan and Chandrasekhar, Arun. “Thermal and power challenges inhighperformancecomputingsystems.”JapaneseJournal of Applied PhysicsVol. 48 No. 5S2 (2009): p. 05EA01

work page 2009
[6]

High flux heat removal with mi- crochannels—a roadmap of challenges and opportunities

Kandlikar, Satish G. “High flux heat removal with mi- crochannels—a roadmap of challenges and opportunities.” Heat Transfer EngineeringVol. 26 No. 8 (2005): pp. 5–14

work page 2005
[7]

Boiling in microchannels: a review of experiment and theory

Thome, John R. “Boiling in microchannels: a review of experiment and theory.”International Journal of Heat and Fluid FlowVol. 25 No. 2 (2004): pp. 128–139

work page 2004
[8]

A practical implementation of silicon microchannel coolers for high power chips

Colgan,EvanG,Furman,Bruce,Gaynes,Michael,Graham, Willian S, LaBianca, Nancy C, Magerlein, John H, Polas- tre, Robert J, Rothwell, Mary Beth, Bezama, RJ, Choud- hary, Rehan et al. “A practical implementation of silicon microchannel coolers for high power chips.”IEEE trans- actionsoncomponentsandpackagingtechnologiesVol.30 No. 2 (2007): pp. 218–225

work page 2007
[9]

A compar- ative analysis of studies on heat transfer and fluid flow in microchannels

Sobhan, Choondal B and Garimella, Suresh V. “A compar- ative analysis of studies on heat transfer and fluid flow in microchannels.”Microscale Thermophysical Engineering Vol. 5 No. 4 (2001): pp. 293–311

work page 2001
[10]

Forced convective heat transfer across a pin fin micro heat sink

Peles, Yoav, Koşar, Ali, Mishra, Chandan, Kuo, Chih-Jung and Schneider, Brandon. “Forced convective heat transfer across a pin fin micro heat sink.”International Journal of Heat and Mass TransferVol. 48 No. 17 (2005): pp. 3615– 3627

work page 2005
[11]

Efficiency of optimized bifurcating tree-like and parallel microchannel networksinthecoolingofelectronics

Escher, W., Michel, B. and Poulikakos, D. “Efficiency of optimized bifurcating tree-like and parallel microchannel networksinthecoolingofelectronics.”InternationalJour- nal of Heat and Mass TransferVol. 52 No. 5-6 (2009): pp. 1421–1432

work page 2009
[12]

Analysisofmicrochannelheatsinks for electronics cooling

Zhao,CYandLu,TJ. “Analysisofmicrochannelheatsinks for electronics cooling.”International Journal of Heat and Mass TransferVol. 45 No. 24 (2002): pp. 4857–4869

work page 2002
[13]

Micro-channel heat exchanger optimization

Harpole,GeorgeM,Eninger,JamesEetal. “Micro-channel heat exchanger optimization.”Proceeding of the 7th IEEE SEMI-THERM Symposium: pp. 59–63. 1991. IEEE

work page 1991
[14]

Optimization study of stacked micro-channel heat sinks for micro-electronic cooling

Wei, Xiaojin and Joshi, Yogendra. “Optimization study of stacked micro-channel heat sinks for micro-electronic cooling.”IEEEtransactionsoncomponentsandpackaging technologiesVol. 26 No. 1 (2003): pp. 55–61

work page 2003
[15]

An additively manufactured manifold- microchannel heat sink for high-heat flux cooling

Kong, Daeyoung, Jung, Euibeen, Kim, Yunseo, Manepalli, Vivek Vardhan, Rah, Kyupaeck Jeff, Kim, Han Sang, Hong,Yongtaek,Choi,HyoungGil,Agonafer,Damenaand Lee, Hyoungsoon. “An additively manufactured manifold- microchannel heat sink for high-heat flux cooling.”Inter- national Journal of Mechanical SciencesVol. 248 (2023): p. 108228

work page 2023
[16]

Additive manufacturing of vapor chambers

Chen, Kuan-Lin, Hsu, Shao-Chi and Kang, Shung-Wen. “Additive manufacturing of vapor chambers.”Materials Vol. 18 No. 5 (2025): p. 979

work page 2025
[17]

Embedded microchannel cooling for high power-density GaN-on-Si power integrated circuits

Van Erp, Remco, Kampitsis, Georgios, Nela, Luca, Arde- bili, Reza Soleimanzadeh and Matioli, Elison. “Embedded microchannel cooling for high power-density GaN-on-Si power integrated circuits.”2020 19th IEEE Intersociety Conference on Thermal and Thermomechanical Phenom- enainElectronicSystems(ITherm): pp.53–59.2020.IEEE

work page 2020
[18]

Generative Design for Direct-to-Chip Liquid Cooling for Data Centers

Liu, Zheng. “Generative Design for Direct-to-Chip Liquid Cooling for Data Centers.”arXiv preprint arXiv:2604.10941(2026)

work page internal anchor Pith review Pith/arXiv arXiv 2026
[19]

Deep Dive into NVIDIA GB200 Liq- uid Cooling Plate Design: Advanced Liquid Cool- ing for AI Chips

FiberMall. “Deep Dive into NVIDIA GB200 Liq- uid Cooling Plate Design: Advanced Liquid Cool- ing for AI Chips.” https://www.fibermall.com/blog/ nvidia-gb200-liquid-cooling-plate.htm (2025). [Accessed 22-03-2026]

work page 2025
[20]

Case-embedded cooling for high heat flux microwavemulti-chiparray

Song, Yunqian, Fu, Rong, Chen, Chuan, Wang, Qidong, Su, Meiying, Hou, Fengze, Zhang, Xiaobin, Li, Jun and Cao, Liqiang. “Case-embedded cooling for high heat flux microwavemulti-chiparray.”AppliedThermalEngineering Vol. 214 (2022): p. 118852. 9 Copyright©2026 by ASME

work page 2022

[1] [1]

High- performanceheatsinkingforVLSI

Tuckerman, David B and Pease, Roger Fabian W. “High- performanceheatsinkingforVLSI.”IEEEElectrondevice lettersVol. 2 No. 5 (2005): pp. 126–129

work page 2005

[2] [2]

High efficiency liquid cooling system of power electronic converter

Liang, Jinhua, Xu, Haiping, Yuan, Zengquan and Zhou, Peng. “High efficiency liquid cooling system of power electronic converter.”2020 5th Asia Conference on Power 8 Copyright©2026 by ASME andElectricalEngineering(ACPEE):pp.1270–1275.2020. IEEE

work page arXiv 2020

[3] [3]

Assessment of high-heat-flux thermal management schemes

Mudawar, Issam. “Assessment of high-heat-flux thermal management schemes.”IEEE transactions on components andpackagingtechnologiesVol.24No.2(2002): pp.122– 141

work page 2002

[4] [4]

Machine learn- ing aided design and optimization of thermal metamateri- als

Zhu, Changliang, Bamidele, Emmanuel Anuoluwa, Shen, Xiangying, Zhu, Guimei and Li, Baowen. “Machine learn- ing aided design and optimization of thermal metamateri- als.”Chemical ReviewsVol. 124 No. 7 (2024): pp. 4258– 4331

work page 2024

[5] [5]

Thermal and power challenges inhighperformancecomputingsystems

Natarajan, Venkat, Deshpande, Anand, Solanki, Sudarshan and Chandrasekhar, Arun. “Thermal and power challenges inhighperformancecomputingsystems.”JapaneseJournal of Applied PhysicsVol. 48 No. 5S2 (2009): p. 05EA01

work page 2009

[6] [6]

High flux heat removal with mi- crochannels—a roadmap of challenges and opportunities

Kandlikar, Satish G. “High flux heat removal with mi- crochannels—a roadmap of challenges and opportunities.” Heat Transfer EngineeringVol. 26 No. 8 (2005): pp. 5–14

work page 2005

[7] [7]

Boiling in microchannels: a review of experiment and theory

Thome, John R. “Boiling in microchannels: a review of experiment and theory.”International Journal of Heat and Fluid FlowVol. 25 No. 2 (2004): pp. 128–139

work page 2004

[8] [8]

A practical implementation of silicon microchannel coolers for high power chips

Colgan,EvanG,Furman,Bruce,Gaynes,Michael,Graham, Willian S, LaBianca, Nancy C, Magerlein, John H, Polas- tre, Robert J, Rothwell, Mary Beth, Bezama, RJ, Choud- hary, Rehan et al. “A practical implementation of silicon microchannel coolers for high power chips.”IEEE trans- actionsoncomponentsandpackagingtechnologiesVol.30 No. 2 (2007): pp. 218–225

work page 2007

[9] [9]

A compar- ative analysis of studies on heat transfer and fluid flow in microchannels

Sobhan, Choondal B and Garimella, Suresh V. “A compar- ative analysis of studies on heat transfer and fluid flow in microchannels.”Microscale Thermophysical Engineering Vol. 5 No. 4 (2001): pp. 293–311

work page 2001

[10] [10]

Forced convective heat transfer across a pin fin micro heat sink

Peles, Yoav, Koşar, Ali, Mishra, Chandan, Kuo, Chih-Jung and Schneider, Brandon. “Forced convective heat transfer across a pin fin micro heat sink.”International Journal of Heat and Mass TransferVol. 48 No. 17 (2005): pp. 3615– 3627

work page 2005

[11] [11]

Efficiency of optimized bifurcating tree-like and parallel microchannel networksinthecoolingofelectronics

Escher, W., Michel, B. and Poulikakos, D. “Efficiency of optimized bifurcating tree-like and parallel microchannel networksinthecoolingofelectronics.”InternationalJour- nal of Heat and Mass TransferVol. 52 No. 5-6 (2009): pp. 1421–1432

work page 2009

[12] [12]

Analysisofmicrochannelheatsinks for electronics cooling

Zhao,CYandLu,TJ. “Analysisofmicrochannelheatsinks for electronics cooling.”International Journal of Heat and Mass TransferVol. 45 No. 24 (2002): pp. 4857–4869

work page 2002

[13] [13]

Micro-channel heat exchanger optimization

Harpole,GeorgeM,Eninger,JamesEetal. “Micro-channel heat exchanger optimization.”Proceeding of the 7th IEEE SEMI-THERM Symposium: pp. 59–63. 1991. IEEE

work page 1991

[14] [14]

Optimization study of stacked micro-channel heat sinks for micro-electronic cooling

Wei, Xiaojin and Joshi, Yogendra. “Optimization study of stacked micro-channel heat sinks for micro-electronic cooling.”IEEEtransactionsoncomponentsandpackaging technologiesVol. 26 No. 1 (2003): pp. 55–61

work page 2003

[15] [15]

An additively manufactured manifold- microchannel heat sink for high-heat flux cooling

Kong, Daeyoung, Jung, Euibeen, Kim, Yunseo, Manepalli, Vivek Vardhan, Rah, Kyupaeck Jeff, Kim, Han Sang, Hong,Yongtaek,Choi,HyoungGil,Agonafer,Damenaand Lee, Hyoungsoon. “An additively manufactured manifold- microchannel heat sink for high-heat flux cooling.”Inter- national Journal of Mechanical SciencesVol. 248 (2023): p. 108228

work page 2023

[16] [16]

Additive manufacturing of vapor chambers

Chen, Kuan-Lin, Hsu, Shao-Chi and Kang, Shung-Wen. “Additive manufacturing of vapor chambers.”Materials Vol. 18 No. 5 (2025): p. 979

work page 2025

[17] [17]

Embedded microchannel cooling for high power-density GaN-on-Si power integrated circuits

Van Erp, Remco, Kampitsis, Georgios, Nela, Luca, Arde- bili, Reza Soleimanzadeh and Matioli, Elison. “Embedded microchannel cooling for high power-density GaN-on-Si power integrated circuits.”2020 19th IEEE Intersociety Conference on Thermal and Thermomechanical Phenom- enainElectronicSystems(ITherm): pp.53–59.2020.IEEE

work page 2020

[18] [18]

Generative Design for Direct-to-Chip Liquid Cooling for Data Centers

Liu, Zheng. “Generative Design for Direct-to-Chip Liquid Cooling for Data Centers.”arXiv preprint arXiv:2604.10941(2026)

work page internal anchor Pith review Pith/arXiv arXiv 2026

[19] [19]

Deep Dive into NVIDIA GB200 Liq- uid Cooling Plate Design: Advanced Liquid Cool- ing for AI Chips

FiberMall. “Deep Dive into NVIDIA GB200 Liq- uid Cooling Plate Design: Advanced Liquid Cool- ing for AI Chips.” https://www.fibermall.com/blog/ nvidia-gb200-liquid-cooling-plate.htm (2025). [Accessed 22-03-2026]

work page 2025

[20] [20]

Case-embedded cooling for high heat flux microwavemulti-chiparray

Song, Yunqian, Fu, Rong, Chen, Chuan, Wang, Qidong, Su, Meiying, Hou, Fengze, Zhang, Xiaobin, Li, Jun and Cao, Liqiang. “Case-embedded cooling for high heat flux microwavemulti-chiparray.”AppliedThermalEngineering Vol. 214 (2022): p. 118852. 9 Copyright©2026 by ASME

work page 2022