{"as_of":"2026-08-09T08:15:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:7701e47177240c3987711f8883c084a54031268d95ce3d791acb6cb96ab649ac","coverage":[{"denominator":49,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":49,"source":"paper_references, paper_reference_links","source_observed_at":"2026-07-15T10:45:43.149976Z","state":"measured"},{"denominator":49,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":49,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-09T06:31:02.800959+00:00","state":"measured"},{"denominator":0,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"cited_works","source_observed_at":null,"state":"measured"}],"external_citation_measurements":[],"inbound":[],"links":{"evidence":"/evidence","html":"/paper/2606.19387/citation-record","integrity":"/paper/2606.19387/integrity","json":"/paper/2606.19387/citation-record.json","paper":"/paper/2606.19387"},"outbound":[{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":1993},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:004f65297e02b424df59da42e65e4c4a92dfc80deb56830c57ae3d38db5af643","observation_id":"97593c71-be0c-4a63-854b-b52cc26f5729","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:0295bd869ac57120072bd1a2289e70458fcfaa12ca680e515f0fbc1ebabba16d","observation_id":"76db1d4f-06e2-4570-8e5e-e64c263698ea","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":"1993.Structured logic design with VHDL","venue":null,"work_id":null,"year":1993},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:601d94cb3c063863a6b74b5e5f9264f4c52f2600477579b644de974fa082f7e9","observation_id":"f643d08c-e84c-481b-92b2-3000ccc001f9","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":"2000.VHDL design representation and synthesis","venue":null,"work_id":null,"year":2000},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:fa38a0d1984a0bc04a7d21cafa83cfb8be96d38b77888089eabf51195bbf3554","observation_id":"eb2338f4-6484-43b9-8f78-0203ab22e4f9","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":1988},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:422949684bae5044de3d1389ddc1d9def7c7011fdec7114ff746cd94429ed582","observation_id":"849dfc63-da28-471b-9e02-21885c9ec5d3","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":1989},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:400374d04bade2ebde81d4b2cae4d36c9aab1dcaf6f1bef63c73908ad0ae1a97","observation_id":"1d9e26ca-8304-4051-8d22-858f9c9fec61","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:fe4a6ccf35f87ef17a7be2b58b0fd2b3497ba0c4f8cce2be240f4b35437cd98f","observation_id":"a62def9e-deea-46ae-8949-ed2e4fc24af3","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":1997},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:687c5be012d1362b92717ed805386be0c50bc46ae778b1c73a17c425fcf23e78","observation_id":"a3a33ab4-c230-4744-acb9-e27786db81d6","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":1995},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:d9038f1244566b178e3311460515d4aac556857da23699f3d840b945496b75e9","observation_id":"7ebca16c-44f7-406b-bd7c-934631592bb7","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":1996},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:c66fe81a84119740d4b09fda910a7a56817c742bbe7359e5c66ca9a1bc5706f2","observation_id":"368f11d3-e92a-4c1b-872e-f0260f206f37","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:d0492b68286e607f9a9d8a1314237bcd6c30f7d9e543405f2f1dde8300013917","observation_id":"60c80cf7-debf-42b9-bd71-dff27777c8d6","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":2026},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:290146b7522309b8449ee722cfbec6b85e2a79ce44b0a66d7963cf72fb139c42","observation_id":"a09bf95b-f9c9-433d-9c58-6cea7188e348","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:36f6541142829849f7ea49b68d8c7a4197ca6372270736b0d4cb916524142073","observation_id":"b9f43173-2093-4eaf-8262-fa77993db451","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":2011},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:064fa9a8d1072cba42f1861c70d07a0766bb9da7787e74406d2fc30d0e56de70","observation_id":"d882bafa-48a0-4dd6-aa87-430cbbd7131f","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":1972},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:ba9c748ee01f31a84dad9c5ef62c68277b769ba8c0b3b7a609f08e43af647d5d","observation_id":"764f73d1-6342-4884-8ffb-132aac33c90c","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":"1976.A discipline of programming","venue":null,"work_id":null,"year":1976},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:4aba1d83d4bad4829465eb2728e49bafd765ee5636980bc17ff67787f057dc29","observation_id":"6f010615-2cda-479a-a8f8-f2ba7258aa33","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":2002},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:d55775a0e3a8e146e776fd3ba0aedd9cab30e3ad006e1efbd3ccc297748c0c61","observation_id":"ff70c152-c7bd-48c1-a30c-b312609ee07f","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:e205b9a2920e1427181417b83072e7ce8b41e4f479bb61cc774cc2ffaf025f24","observation_id":"fd0190bc-9a09-47ad-898a-690ccc644529","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:05d6fe4d9b9c8f952bd9fa73bef56d246b7c275c1a0b3f0a027917fa67149e19","observation_id":"b6dcb505-6f6e-455e-872d-3331269f86a5","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":2001},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:d4919ca2aadc40b979e0995d7a93ebdf10a9be8415e08e9fc7a49dc6200292fa","observation_id":"fc3b6d49-1620-4639-80d0-bd634cc4d4f5","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":21,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:29cc60e8ea4c686309de0ea9e3e2077476cb5684a5eadc483711d8ab0af582dd","observation_id":"08619b99-dd29-4625-82d7-cc3a13038bed","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:848b415b155b1621a59df55ede135ca55ca9e26105472d44b33da5669edc93f4","observation_id":"2db11558-34f1-4cd1-a329-efe7583cb9c5","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2406.00115","last_updated":"2024-05-31T18:06:15Z","snapshot_observed_at":"2026-07-06T18:23:31.520359Z","submitted_at":"2024-05-31T18:06:15Z","title":"Towards LLM-Powered Verilog RTL Assistant: Self-Verification and Self-Correction","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2406.00115","snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":23,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"cited_paper":"/paper/2406.00115","citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:d60c0790b87f2a7a2b69af850f913706e1e08043adf333931170390d14e6d82a","observation_id":"4489cdac-83fa-4611-b8a6-05c136d689a7","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":1983},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":24,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:d7529eb5f92618ef73ccd85a7c050e6451ff25387e0863132523c2190a0846ca","observation_id":"a571b74a-954d-4c7c-b659-654ee273de2b","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"1606.02022","last_updated":"2016-06-07T04:09:44Z","snapshot_observed_at":"2026-08-04T05:52:55.853474Z","submitted_at":"2016-06-07T04:09:44Z","title":"Programming Language Features for Refinement","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"1606.02022","snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":2016},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":25,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"cited_paper":"/paper/1606.02022","citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:0e2051b36672699ba9b43ce2be1d71b43c78156c4612907db397da563e83806b","observation_id":"ca65c3c5-c06a-4bbb-99f3-df7ee92cd144","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":26,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:2a78982caee48fdabe9825268fb9fca04237ae4cd87c0e3275f0cc08b13fa318","observation_id":"4732c1e7-441b-4644-98fb-b07223d292bd","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":2010},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":27,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:e892e467c118d46562231b31829169ffb68ca7b1eb187f145016beaa3b36461b","observation_id":"bb155fd3-3ec7-479e-9ec8-2861274fdd9c","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":1992},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":28,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:55906562317b462518863260399201d179c8beb35f9412683c6cfe9b7e1d31eb","observation_id":"76a42375-c5de-4da2-aad9-8ec2e6176eb9","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":1990},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":29,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:19d8cc9f66bac146c938576f522ee7cc44d6d42d9d0dd8575e3444f2e5a7c223","observation_id":"18191a90-cd09-408f-b9ca-9299137556d1","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":2010},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":30,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:edb6ff9ddceb9799da51c6051dd6e47aaee670b191022d34b19fffde371e60f3","observation_id":"c041f830-45ff-45f7-a18a-2d4c2a5cee61","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":1988},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":31,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:bd26dc1e01b46dfd53057153b12b06f316146a922b3c65fc86fb1fb468332381","observation_id":"2082c108-5b2d-4efd-b005-22ea8c5dc45a","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":"1990.Programming from specifications","venue":null,"work_id":null,"year":1990},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":32,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:0e30289b4efc16aa1cbdab7d3bbf6700c7fce3229363fc9901c963200636565c","observation_id":"3ba3d9cf-0879-46ec-826a-1873dd0d65e5","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":1987},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":33,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:102fcd29e699d0e03d2898ea22dfbc9c50a126406c6f50d1cc357eab8886879d","observation_id":"01a95902-6480-4bf3-b977-9813cdd38115","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":34,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:482485c0426ac6aa614eee6c1d0121d36cfd3c6e58298aadc6733b061bca65d4","observation_id":"1a81dd04-77d7-449b-9077-e5ddeab65a59","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2506.14074","last_updated":"2025-06-17T00:11:13Z","snapshot_observed_at":"2026-08-07T00:16:05.924830Z","submitted_at":"2025-06-17T00:11:13Z","title":"Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2506.14074","snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":35,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"cited_paper":"/paper/2506.14074","citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:eea5c028aa2a813eedf237a28d30bda72c5504d164280451c39e944557cc3e94","observation_id":"222552d4-52ea-4ec0-abce-269bc2e165ce","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":"1996.Requirements engineering: An overview","venue":null,"work_id":null,"year":1996},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":36,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:f323e3bc16f2c15ad253809186c9604fa5a51e3997a088bc0327fccabf9d4557","observation_id":"1454d161-5fda-4d97-83e6-1cfd2efce7c0","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":2014},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":37,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:9b275db64481ade3e1a5a40b8caa7b17b8e8a8f3426776e472394b54b498fc52","observation_id":"aec39c26-063f-4728-900c-de99403d9f62","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":38,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:5ac97eb2202f1ac2df25bb1821d347fffd51f3c2ac52d1bde0d6026a033673c3","observation_id":"243e3547-4647-4684-bf5d-8742a0c07cf2","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":1996},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":39,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:32f210a6c1dc3745c122fb2a797b3f04b4a1c673168499443cf1e3be18ce8d04","observation_id":"f493dba4-329b-4f75-90e4-a3990cf05a12","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":1998},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":40,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:53f06b5792b53ed425727e489a7b21ec4112bdf5ec5f50f3e1448f22f7a3b628","observation_id":"b3a6f1ed-3f0e-4d92-9b09-b04febd87e4a","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":1996},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":41,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:3ef59229a91c02f9a9de62176f9c1ced7fa5c4ababaeb3a55f2f85f592e4b4d3","observation_id":"ee2e27bd-bf8c-436e-88f9-c6682c1157b8","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2311.04887","last_updated":"2024-06-04T19:12:48Z","snapshot_observed_at":"2026-08-05T17:48:12.430235Z","submitted_at":"2023-11-08T18:46:39Z","title":"AutoChip: Automating HDL Generation Using LLM Feedback","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2311.04887","snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":42,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"cited_paper":"/paper/2311.04887","citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:abca5337201862ebf41664bde4518b222d0ab21e81ff82ac2bb2f75f9edd65dc","observation_id":"f2d28ebf-2a42-48dc-aad0-285427d3f170","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":43,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:aff8681fa7c57bb2d5216782512f89913ed5793c22753b0771a7ba1f33bee970","observation_id":"09a11642-f05b-4959-b406-d5ac59eac08b","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2505.11849","last_updated":"2025-05-17T05:25:01Z","snapshot_observed_at":"2026-08-07T15:44:24.448694Z","submitted_at":"2025-05-17T05:25:01Z","title":"VeriReason: Reinforcement Learning with Testbench Feedback for Reasoning-Enhanced Verilog Generation","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2505.11849","snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":44,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"cited_paper":"/paper/2505.11849","citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:73497fa652ba15ec0ab5dfbfce40e37b27188a356971d648578f647b39086ec9","observation_id":"9a616aba-dc5f-4eb0-9a63-aea34be02a94","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":1971},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":45,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:d56addf806fb8ef6fc52d95f9cc06827ef4bedb72858544a1c0c44a7dd48384f","observation_id":"368927cf-1541-49c2-b3ee-c191b2c0c5ff","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":2013},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":46,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:e9ce1e3b60ef63b745875c94a24fdcf58211af4ae143b799fdc16602248d1c88","observation_id":"4e9e3e0d-8a5a-44c8-a506-cec5122dbeb8","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":47,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:f54207a2348bf4c5945b39046d62e23d2254780195255f127268a0b578b2c0a8","observation_id":"0b37c015-d8ee-46e6-a22c-de5ed4dab232","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":null,"venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":48,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:17fc966f0c3fcfe0d583788d97620099913d7dbc57a6dd06f55d2e54b9e8cd64","observation_id":"bee30019-fca2-42eb-9c74-1265105de436","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-07-15T10:45:43.149976Z","title":"Iteration","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement","version":2},"reference_index":49,"source":"pdf_text","source_observed_at":"2026-07-15T10:45:43.149976Z"},"links":{"citing_paper":"/paper/2606.19387"},"observation_digest":"sha256:49942d3521c1fed455406adb1c29c890fdc9ee078f9fc469031921cc3cb7d663","observation_id":"e47e6512-baa8-481e-b0cd-68d31073892d","resolution":{"observed_at":"2026-07-15T10:45:43.149976Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}}],"paper":{"arxiv_id":"2606.19387","last_updated":"2026-07-13T22:54:14Z","latest_version":2,"primary_category":"cs.SE","snapshot_observed_at":"2026-08-01T07:45:29.111140Z","submitted_at":"2026-06-16T01:28:22Z","title":"Interpretable and Verifiable Hardware Generation with LLM-Driven Stepwise Refinement"},"reference_resolution":{"displayed":49,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":49,"verified_exact":0,"verified_fuzzy":0},"total_outbound_references":49},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-09T06:31:02.800959+00:00","source":"crossref"},{"observed_at":"2026-08-09T06:30:57.326959+00:00","source":"retraction_watch"}],"thesis":"As of 9 August 2026, this Paper Citation Record lists 49 of 49 outbound references and 0 inbound Pith citation observations for arXiv:2606.19387."}