{"as_of":"2026-08-09T05:43:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:8346198e0b0ed0fea593521467e20bbea46901e237c3e2bad51da2cc3bc8ade3","coverage":[{"denominator":36,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":36,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-02T00:17:24.756369Z","state":"measured"},{"denominator":36,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":36,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-08T06:32:00.761636+00:00","state":"measured"},{"denominator":0,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"cited_works","source_observed_at":null,"state":"measured"}],"external_citation_measurements":[],"inbound":[],"links":{"evidence":"/evidence","html":"/paper/2607.15068/citation-record","integrity":"/paper/2607.15068/integrity","json":"/paper/2607.15068/citation-record.json","paper":"/paper/2607.15068"},"outbound":[{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.616455Z","title":"Stiff circuit system modeling via transformer,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.616455Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:ed3cf7fa0ceba7affe3ee2f050147b7b604a8b44a1c3465f54089438806ae12c","observation_id":"378ffafd-f606-491b-9152-69f8ff9fb3bd","resolution":{"observed_at":"2026-08-02T00:17:24.616455Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.621210Z","title":"Labeling cost sensitive batch active learning for brain tumor segmentation,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.621210Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:c44f514eb58486db5fef4217f7f52f8d15a276cd1d0bb8b235754289e6f72acf","observation_id":"6a1f8dce-96c4-4a08-8b77-9ce773d9c3c6","resolution":{"observed_at":"2026-08-02T00:17:24.621210Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.625215Z","title":"Patternpaint: Practical layout pattern generation using diffusion-based inpainting,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.625215Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:f7dad2ab6c7f653bb34922c86dc2761c8af90d51d6d0a2823325240ce165b02b","observation_id":"a962b6c3-a879-48c5-a3d9-7e34f7c2cf94","resolution":{"observed_at":"2026-08-02T00:17:24.625215Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.629526Z","title":"Diffusion- model-enhanced layout pattern generation for sub-3nm dfm,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.629526Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:5100f2a1072d77de748583f65f8794bc9bc646d47e00d10076dc72921ea061a7","observation_id":"4f917b3a-372b-4185-b296-1ac825b77bb3","resolution":{"observed_at":"2026-08-02T00:17:24.629526Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.634349Z","title":"Dark silicon and the end of multicore scaling,","venue":null,"work_id":null,"year":2011},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.634349Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:bb3535c74c95d0658872c67181c9a14e323a1480d8b114e528fd1c813a7ef275","observation_id":"f028c881-6169-40cf-8cb0-92941eb52ae8","resolution":{"observed_at":"2026-08-02T00:17:24.634349Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.638519Z","title":"A reconfigurable fabric for accelerating large-scale datacenter services,","venue":null,"work_id":null,"year":2014},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.638519Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:f56a44502fe09b45a7534616f3bbe8ad7127c236271576976d8e0cba95e79df8","observation_id":"9c61af0a-1f87-48f3-924a-e4c306ced814","resolution":{"observed_at":"2026-08-02T00:17:24.638519Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.643148Z","title":"A cloud-scale acceleration architecture,","venue":null,"work_id":null,"year":2016},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.643148Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:232c3653a05e7639c88fa5d18be9688fbfc9cca8b17be2ce1608c5c34efacfad","observation_id":"198c0bc9-ac30-4cd7-9d60-9c1cd76e7863","resolution":{"observed_at":"2026-08-02T00:17:24.643148Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.647108Z","title":"FPGA HLS today: Successes, challenges, and opportunities,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.647108Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:ab3285577b6f40c4dae9bce1f026b765e6f567e4fe417c3f97a6500ccccb6fb8","observation_id":"0d8db604-7992-42cf-87ab-969635bb4d95","resolution":{"observed_at":"2026-08-02T00:17:24.647108Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.651663Z","title":"High-level synthesis design space explo- ration: Past, present, and future,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.651663Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:546f8fac43159be9935e686da0e0acd2f011cbb4e7833d3c453a9366a453cc70","observation_id":"cc300a7b-0064-4c30-9236-12db74c7eabb","resolution":{"observed_at":"2026-08-02T00:17:24.651663Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.655707Z","title":"Allo: A programming model for composable accelerator design,","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.655707Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:f0798f3a36bd60556883579ad0fa45698ae58d5f26dfa56810d2eb127fd93603","observation_id":"d22894bf-4280-43bd-814f-0bf2401e0285","resolution":{"observed_at":"2026-08-02T00:17:24.655707Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.659883Z","title":"The landscape of parallel computing research: A view from Berkeley,","venue":null,"work_id":null,"year":2006},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.659883Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:874759fc8d5b81fe230f6ef385557ce79d7b27928fad3be5c96c43e8eee78bca","observation_id":"ca7a63a8-de96-4bdc-a64e-515179bf83bb","resolution":{"observed_at":"2026-08-02T00:17:24.659883Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.663798Z","title":"MachSuite: Benchmarks for accelerator design and customized architectures,","venue":null,"work_id":null,"year":2014},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.663798Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:fcc857615ee855f2fea5853fb9f3406295654ba77f027d49e0345ecb99923f60","observation_id":"ec6b33dd-5bde-49a7-a937-88bb6f6c3be6","resolution":{"observed_at":"2026-08-02T00:17:24.663798Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.668133Z","title":"Rodinia: A benchmark suite for heterogeneous computing,","venue":null,"work_id":null,"year":2009},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.668133Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:7b24bbbb481ac2169877d6aa7b2c097f34390dda7b636bb535eedc76589e2cc6","observation_id":"17460494-0aa9-4f0a-bbfd-a5bcfd233868","resolution":{"observed_at":"2026-08-02T00:17:24.668133Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.671685Z","title":"CHStone: A benchmark program suite for practical C-based high-level synthesis,","venue":null,"work_id":null,"year":2008},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.671685Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:1f0218fe6fd8b8497533b74038236b4345fb54129e58dd8ca56bca4f31e20c67","observation_id":"1f609b53-e036-4c72-b597-a09a417ac139","resolution":{"observed_at":"2026-08-02T00:17:24.671685Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.675682Z","title":"Rosetta: A realistic high-level synthesis benchmark suite for software programmable FPGAs,","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.675682Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:354a52cad0d0434f499f0b13fe29652a8f66152de5326e9886b4e11dcd3671bc","observation_id":"718b57ff-d4b4-4c6e-a00b-83f8d4addd0e","resolution":{"observed_at":"2026-08-02T00:17:24.675682Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.679406Z","title":"MLPerf inference benchmark,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.679406Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:f3719dcad7fa1ce9c0f651067f2a5e0aa79c66a266a646563bf9574c69eacfaf","observation_id":"a85f4013-f31a-4eb6-a41c-3bcd1b77acb1","resolution":{"observed_at":"2026-08-02T00:17:24.679406Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.683062Z","title":"ScaleHLS: A scalable high-level synthesis framework with multi-level transforma- tions and optimizations,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.683062Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:b5520ec587ff782e6e6911507dc83b592f661c81cd6c37e7ce8557b7f522d9cc","observation_id":"09740543-f3bb-45af-8e2d-60b5146bbdc0","resolution":{"observed_at":"2026-08-02T00:17:24.683062Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.686860Z","title":"Decoupling algorithms from schedules for easy optimization of image processing pipelines,","venue":null,"work_id":null,"year":2012},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.686860Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:e3b9e09d764cf6b57ca7406b7ef9f34f1a11c38a79552426ee66dee6862f882b","observation_id":"191058f6-bdd5-4ffb-a1e0-1216521ae684","resolution":{"observed_at":"2026-08-02T00:17:24.686860Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.690537Z","title":"TVM: An automated end-to-end optimizing compiler for deep learning,","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.690537Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:1a7dd4bc338d1fe5e7306e7fc2389a29562cc9260793f987ac1bd80f1898569c","observation_id":"25602d2a-73f3-4e92-8cf1-5c7a0ca62f6e","resolution":{"observed_at":"2026-08-02T00:17:24.690537Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.694110Z","title":"HeteroCL: A multi-paradigm programming infrastructure for software-defined reconfigurable computing,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.694110Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:bfc1a55b64717ebd2dec9c39d75667bca48bbfa705982980e5fa4f62cd14abdc","observation_id":"0b5850d9-3e51-48c6-b583-5b4d2de8a59d","resolution":{"observed_at":"2026-08-02T00:17:24.694110Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.698711Z","title":"fpgaConvNet: A framework for mapping convolutional neural networks on FPGAs,","venue":null,"work_id":null,"year":2016},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":21,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.698711Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:86fa411f4f631ba8a486b630c72f2695b8d9734d1f609c355c56e651d3253778","observation_id":"9c80d0d9-ad0d-462a-b72e-56f4e0c8b7d3","resolution":{"observed_at":"2026-08-02T00:17:24.698711Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.702515Z","title":"DNNBuilder: An automated tool for building high-performance DNN hardware accelerators for FPGAs,","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.702515Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:73564857a0a44ec657435b1cd096a267aa629f82072ef717e8b36f6019c1f42d","observation_id":"fb874a9a-35d3-4976-887a-a12f40051b41","resolution":{"observed_at":"2026-08-02T00:17:24.702515Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.706434Z","title":"In-datacenter performance analysis of a tensor processing unit,","venue":null,"work_id":null,"year":2017},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":23,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.706434Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:3a44bbe28563e12961c827fe6bebc6c51768808deddce194cb0707cb9dd89a42","observation_id":"fa761949-cffc-4757-adc7-416213ccc13c","resolution":{"observed_at":"2026-08-02T00:17:24.706434Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.710251Z","title":"Gemmini: Enabling systematic deep-learning archi- tecture evaluation via full-stack integration,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":24,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.710251Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:0a58de3e50b8243e5ed70494eb75befbe694cd1d95d436c9fca94029c8764f95","observation_id":"d1c38035-6d82-4be7-9b27-f0fb37943058","resolution":{"observed_at":"2026-08-02T00:17:24.710251Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.713826Z","title":"LegUp: High-level synthesis for FPGA-based processor/accelerator systems,","venue":null,"work_id":null,"year":2011},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":25,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.713826Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:28a8d6443c83fea5dba0845f5f43eb546912c62f4a602f225880c90e1e83daa8","observation_id":"684f6316-c0d1-4eb0-a77e-246ed03778c9","resolution":{"observed_at":"2026-08-02T00:17:24.713826Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2002.11054","last_updated":"2020-03-01T00:38:46Z","snapshot_observed_at":"2026-08-08T19:43:09.940097Z","submitted_at":"2020-02-25T17:24:50Z","title":"MLIR: A Compiler Infrastructure for the End of Moore's Law","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2002.11054","snapshot_observed_at":"2026-08-02T00:17:24.717495Z","title":"MLIR: A compiler infrastructure for the end of Moore’s law,","venue":null,"work_id":null,"year":2002},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":26,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.717495Z"},"links":{"cited_paper":"/paper/2002.11054","citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:5a82fc6395f188fdb7716dfe84ddf1c52e4268e5ed6f68890331d09a330f8afb","observation_id":"30668b16-dfad-42ab-807e-c86f460a439f","resolution":{"observed_at":"2026-08-02T00:17:24.717495Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.721376Z","title":"VTR 7.0: Next generation architecture and CAD system for FPGAs,","venue":null,"work_id":null,"year":2014},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":27,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.721376Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:33e807ac0cb7b9f15d9be9e939a1ac10434ed07ce3c521bbfedd3e71eb868c70","observation_id":"9161ff0c-ee36-468c-9fd3-9efaa229c068","resolution":{"observed_at":"2026-08-02T00:17:24.721376Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.725168Z","title":"AutoBridge: Coupling coarse-grained floorplanning and pipelining for high-frequency HLS design on multi-die FPGAs,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":28,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.725168Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:10d6c27c5dd00eba22cbe4dcfa60d7d8056ebe3cbeb458cb4c0b478dcd5cd541","observation_id":"ac3d45c8-9819-425b-bba7-45e074e48eeb","resolution":{"observed_at":"2026-08-02T00:17:24.725168Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.729014Z","title":"TAPA: A scalable task-parallel dataflow programming framework for modern FPGAs with co-optimization of HLS and physical design,","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":29,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.729014Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:4b8bbc1f2afeb1a24acdb08b83a686ebff0f34ed045764919ee8e46c15c890d3","observation_id":"1aff14d2-78fd-4a3a-b581-6af46fcee82c","resolution":{"observed_at":"2026-08-02T00:17:24.729014Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.732720Z","title":"Chisel: Constructing hardware in a Scala embedded language,","venue":null,"work_id":null,"year":2012},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":30,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.732720Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:121bfd01e5ac8e32f456147e5c3575a229d6e9538e815c3510da39bc1b0a37bc","observation_id":"40d5d297-2483-4f1c-9fb9-6833534d845f","resolution":{"observed_at":"2026-08-02T00:17:24.732720Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.736677Z","title":"OpenROAD: Toward a self-driving, open-source digital layout implementation tool chain,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":31,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.736677Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:122a11f4c5e7fb4bc06a11c2152f07fc85cc2b03a20bc4b87c15efd4e9c232f3","observation_id":"7b91fdbf-250c-48ee-babb-99e60df2bef4","resolution":{"observed_at":"2026-08-02T00:17:24.736677Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.740448Z","title":"On learning-based methods for design- space exploration with high-level synthesis,","venue":null,"work_id":null,"year":2013},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":32,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.740448Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:468f23e0c5db887591f9eab03abe667ab26c19c6dc726d07524af5388934f527","observation_id":"61314dd7-229e-4dfc-af6a-95794cd5bfe5","resolution":{"observed_at":"2026-08-02T00:17:24.740448Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.744196Z","title":"AutoDSE: Enabling software programmers to design efficient FPGA accelerators,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":33,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.744196Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:d20a766c5117821a6115be6beedf1fadf7dd66346387233a981dd1dffd535da9","observation_id":"0cbee2a1-e13c-4a78-8439-42d9a813cc79","resolution":{"observed_at":"2026-08-02T00:17:24.744196Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.747896Z","title":"From predict to generate: A cross-layer survey of generative ai for ic design and manufacturing,","venue":null,"work_id":null,"year":2026},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":34,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.747896Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:a130389098f7ed8e5fa001dbd98db27a3818304824219fdd3ead4443d9b9785a","observation_id":"4245a5a1-9cab-4597-bf05-4f159bb1d820","resolution":{"observed_at":"2026-08-02T00:17:24.747896Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.752237Z","title":"Toward engineering agi: Benchmarking the engineering design capabilities of llms,","venue":null,"work_id":null,"year":null},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":35,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.752237Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:32bd6cce56f1347a1229712155ac81d138833a4785ecd2a5737376cae09af7df","observation_id":"a5db22e7-d50b-4321-88ee-39af16fe3e46","resolution":{"observed_at":"2026-08-02T00:17:24.752237Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-02T00:17:24.756369Z","title":"Available: https://proceedings.neurips.cc/paper files/ paper/2025/file/664f777548205fb6e0cbb0965e8d2e16-Paper-Datasets and Benchmarks Track.pdf","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design","version":1},"reference_index":2025,"source":"pdf_text","source_observed_at":"2026-08-02T00:17:24.756369Z"},"links":{"citing_paper":"/paper/2607.15068"},"observation_digest":"sha256:cf8e697af067aa2592b58298fbb0fe2608c55055b204ceea6943f81058ecb5a7","observation_id":"202d4c09-bd87-4c62-b668-f24875144dc3","resolution":{"observed_at":"2026-08-02T00:17:24.756369Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}}],"paper":{"arxiv_id":"2607.15068","last_updated":"2026-07-16T14:41:17Z","latest_version":1,"primary_category":"cs.AR","snapshot_observed_at":"2026-08-02T00:17:24.165418Z","submitted_at":"2026-07-16T14:41:17Z","title":"Pattern-Guided Design Space Exploration for FPGA Accelerator Design"},"reference_resolution":{"displayed":36,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":36,"verified_exact":0,"verified_fuzzy":0},"total_outbound_references":36},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-08T06:32:00.761636+00:00","source":"crossref"},{"observed_at":"2026-08-08T06:31:55.24221+00:00","source":"retraction_watch"}],"thesis":"As of 9 August 2026, this Paper Citation Record lists 36 of 36 outbound references and 0 inbound Pith citation observations for arXiv:2607.15068."}