{"as_of":"2026-08-09T11:39:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:52d3cabf05d46add14ed7cd090256ef7d12b61232d3dd9920be43af7126fa53c","coverage":[{"denominator":37,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":37,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-01T22:23:40.608907Z","state":"measured"},{"denominator":37,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":37,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-09T06:31:02.800959+00:00","state":"measured"},{"denominator":0,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"cited_works","source_observed_at":null,"state":"measured"}],"external_citation_measurements":[],"inbound":[],"links":{"evidence":"/evidence","html":"/paper/2607.15782/citation-record","integrity":"/paper/2607.15782/integrity","json":"/paper/2607.15782/citation-record.json","paper":"/paper/2607.15782"},"outbound":[{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T22:23:37.976077Z","title":"Differential Power Analysis,","venue":null,"work_id":null,"year":1999},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:37.976077Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:a74950bb41f0e725708a618898e002dcfea91ab3bf5b4061ddcdea2f70d152e6","observation_id":"dbb1010b-1d82-43e5-809c-8912a8967487","resolution":{"observed_at":"2026-08-01T22:23:37.976077Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1007/3-540-44709-1_21","metadata_source":"openalex","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Electromagnetic Analysis: Concrete Results,","venue":"Lecture notes in computer science","work_id":"c9c864d9-13f4-4b84-91ec-6b0bebb7f711","year":2001},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:38.076773Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:477fec0e2fed5e2888ac39ca7d6061f0cec8ede65fa81ee5cce052369fdb7a37","observation_id":"8d03e321-546b-444d-b14f-dff75b441fb1","resolution":{"observed_at":"2026-08-01T22:28:34.234819Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-09T06:31:02.800959+00:00","source":"crossref"},{"observed_at":"2026-08-09T06:30:57.326959+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T22:23:38.211184Z","title":"Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems,","venue":null,"work_id":null,"year":1996},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:38.211184Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:e1a3f136cacfa88d92dd2fcb16ea8be4e9f3d5e6011fe916cc02fdd49f16264a","observation_id":"74e0f170-15b2-42c9-a28c-a62b4d3b96c8","resolution":{"observed_at":"2026-08-01T22:23:38.211184Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T22:23:38.388224Z","title":"EUCLEAK","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:38.388224Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:69b3519dcd30ef610f3e63cd084afd56c9f40e1e5a6ec7d7d6c828ee58656b51","observation_id":"09e18f00-56cb-463c-a5e3-1dcbfecc3359","resolution":{"observed_at":"2026-08-01T22:23:38.388224Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T22:23:38.473627Z","title":"Side-Channel Resis - tance","venue":null,"work_id":null,"year":2026},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:38.473627Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:36e1f105d6dcbc156ca98296263f4e3aac49124738ad0504b59c3acfea28646c","observation_id":"d5adb7f7-fe8f-4313-ba99-ed374f1ec3ff","resolution":{"observed_at":"2026-08-01T22:23:38.473627Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T22:23:38.531326Z","title":"A testing methodology for side-channel resistance validation,","venue":null,"work_id":null,"year":2011},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:38.531326Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:60209fbf4796248b85ecf1998aa183d205b17773cd07790337f999c575dd4f13","observation_id":"52760291-24dd-4809-84c0-7388abaab8fb","resolution":{"observed_at":"2026-08-01T22:23:38.531326Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T22:23:38.564084Z","title":"Coco: Co- Design and Co-Verification of Masked Software Implementations on CPUs,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:38.564084Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:6ec3c09b7440e5d1c477c0177cf9d2ebc5df07e4d84105cd54680a7cda5b9937","observation_id":"4b060951-4bbf-4db3-a49b-976fdc642d55","resolution":{"observed_at":"2026-08-01T22:23:38.564084Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T22:23:38.652889Z","title":"Architecture Corre - lation Analysis (ACA): Identifying the Source of Side-channel Leakage at Gate-level","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:38.652889Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:cf4d6d850cd6e1353836bd6b335bd2af936c7136e57f83f68c93faf8fec9f7ab","observation_id":"bf1c4b3b-a412-486a-9fd5-37c7248fac61","resolution":{"observed_at":"2026-08-01T22:23:38.652889Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1007/s11227-021-03927-w","metadata_source":"openalex","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Power side-channel leakage assessment and locating the exact sources of leakage at the early stages of ASIC design process,","venue":"The Journal of Supercomputing","work_id":"99554d7b-fbdf-4b44-a0e7-feb35b0dead4","year":2022},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:38.708858Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:4887edb4a440f3f7d82a84e524e3abb80c3fb864a3458017b20ed0ed361081ed","observation_id":"46af94f3-54e2-4092-83c5-261eb6d21d99","resolution":{"observed_at":"2026-08-01T22:28:33.974941Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-09T06:31:02.800959+00:00","source":"crossref"},{"observed_at":"2026-08-09T06:30:57.326959+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T22:23:38.773858Z","title":"IEEE standard for Verilog hardware description language (IEEE 1364-2005),","venue":null,"work_id":null,"year":2005},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:38.773858Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:73804ca4b08d2e17ae6e3386fba118c2c1eb5af1927ee4f196bb0af3f174253d","observation_id":"4358cee0-9453-4cc3-a2fd-890c784e1950","resolution":{"observed_at":"2026-08-01T22:23:38.773858Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T22:23:38.831712Z","title":"IEEE Standard for Design and Verification of Low-Power Inte - grated Circuits","venue":null,"work_id":null,"year":2026},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:38.831712Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:2e54cf7f00085b9db4932f4c9844b43b08f12c99e503be32810e0409bae92266","observation_id":"e9b74efa-0efa-4816-843a-84ba4009ffd0","resolution":{"observed_at":"2026-08-01T22:23:38.831712Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T22:23:38.884845Z","title":"FST Format Specification","venue":null,"work_id":null,"year":null},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:38.884845Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:142b0105beecc7a8b24b0ca512d4f78bfa479320777c6b15f3ea1a04f98a9dec","observation_id":"f60ebff2-9e03-4ba1-8307-73bb808c73ea","resolution":{"observed_at":"2026-08-01T22:23:38.884845Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T22:23:38.933395Z","title":"RTL to transistor level power modeling and estimation techniques for FPGA and ASIC: A survey,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:38.933395Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:0ef109c795b874b5cf473e2a66c64ca26743a43cc0dc4c1ab67f144512cc3cfe","observation_id":"346c7160-636b-4642-b3fe-5545685a647e","resolution":{"observed_at":"2026-08-01T22:23:38.933395Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T22:23:38.999648Z","title":"Telescope: Top-Down Hierarchical Pre-silicon Side-channel Leakage Assessment in System- on-Chip Design,","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:38.999648Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:e6017255209b7be3cbe87b7b133f5b13d9a1952eeb23f94deb01b50f2696d0c0","observation_id":"70c08ce5-4e7d-412a-a7df-e42e70333ca9","resolution":{"observed_at":"2026-08-01T22:23:38.999648Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1007/11545262_12","metadata_source":"openalex","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Successfully attacking masked AES hardware implementations,","venue":"Lecture notes in computer science","work_id":"71eda6d3-4c0a-4645-9046-66605927b173","year":2005},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:39.054357Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:17282302b2da114367b4289778c3539a603bd5d50d99de0908c7f3997f72d5ad","observation_id":"c21d0e11-c604-4177-9b69-5e46289efb11","resolution":{"observed_at":"2026-08-01T22:28:33.784989Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-09T06:31:02.800959+00:00","source":"crossref"},{"observed_at":"2026-08-09T06:30:57.326959+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T22:23:39.110346Z","title":"Icarus verilog: open-source verilog more than a year later,","venue":null,"work_id":null,"year":2002},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:39.110346Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:bdbf1dd552c87aaa093834a399fb9d09fbabce339d5d32d21294ae0d0464f5c3","observation_id":"b0660b41-af42-41c3-8fd5-ad96937bcba9","resolution":{"observed_at":"2026-08-01T22:23:39.110346Z","resolver_source":null,"status":"malformed_identifier"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T22:23:39.209890Z","title":"Verilator","venue":null,"work_id":null,"year":2026},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:39.209890Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:2d7a51342a7df1c463a7b8e327f419db3c95ebe97853b579a89cae7b61269c4d","observation_id":"fdb8ba95-e158-4736-ae95-e2a04cd5ced8","resolution":{"observed_at":"2026-08-01T22:23:39.209890Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T22:23:39.285358Z","title":"Cocotb: a Python-based digital logic verification frame - work","venue":null,"work_id":null,"year":null},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:39.285358Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:cd4bb1d10345ca0df94c7d7cde5a540ea9d5cf1190c15609a7b483da91654e25","observation_id":"bb4631ea-97b6-44f7-81fd-e476f8b90d3d","resolution":{"observed_at":"2026-08-01T22:23:39.285358Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T22:23:39.367616Z","title":"Online template attacks,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:39.367616Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:59964c81ed22424cafccc90d8d95acae2e6b4889c7c5b612c7b5c8c753e2e01b","observation_id":"3de49759-b6a4-43c0-9263-2dbcf5fc0247","resolution":{"observed_at":"2026-08-01T22:23:39.367616Z","resolver_source":null,"status":"malformed_identifier"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"1603.08059","last_updated":"2018-01-12T21:18:07Z","snapshot_observed_at":"2026-07-06T04:50:46.411446Z","submitted_at":"2016-03-26T00:25:37Z","title":"CVC Verilog Compiler -- Fast Complex Language Compilers Can be Simple","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"1603.08059","snapshot_observed_at":"2026-08-01T22:23:39.449032Z","title":"CVC Verilog Compiler – Fast Complex Language Compilers Can be Simple","venue":null,"work_id":null,"year":2026},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:39.449032Z"},"links":{"cited_paper":"/paper/1603.08059","citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:d6543fc89beb91fa800ee1393ac1f8583df922a114eb9ec8a70812b1e0c78b11","observation_id":"b7856683-bc4a-4cee-9c8c-d1a15060ec52","resolution":{"observed_at":"2026-08-01T22:23:39.449032Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T22:23:39.506913Z","title":"Yosys - A Free Verilog Synthesis Suite","venue":null,"work_id":null,"year":null},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":21,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:39.506913Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:034c739e914672a7a0a362211171bbbef216d6d9ce54977cea0c13bfbcfd4ca6","observation_id":"12833072-8346-4bfe-8722-0d78e650c9da","resolution":{"observed_at":"2026-08-01T22:23:39.506913Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T22:23:39.596934Z","title":"Openroad: Toward a self-driving, open-source digital layout implementation tool chain,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:39.596934Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:8fd3bc6f1f0ec1ec8c14a2b1d5c23108c7ecd9c10f0d47de173fa56427b790ea","observation_id":"cafe9613-dff3-40b7-9d03-ff31644d2be6","resolution":{"observed_at":"2026-08-01T22:23:39.596934Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1007/978-3-031-98685-7_19","metadata_source":"openalex","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Surfer — An Extensible Waveform Viewer,","venue":"Lecture notes in computer science","work_id":"6b63f569-c47f-412c-8e36-d64c89b3981c","year":2025},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":23,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:39.686789Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:d7d91ba8f1f059faa6dc68f3d86c22e75be20eaf93f3613a621663e39ce6c013","observation_id":"6c693a86-01d5-427b-af94-a517c17fed44","resolution":{"observed_at":"2026-08-01T22:28:33.564753Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-09T06:31:02.800959+00:00","source":"crossref"},{"observed_at":"2026-08-09T06:30:57.326959+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T22:23:39.740716Z","title":"MLIR: Scaling Compiler Infrastructure for Domain Specific Computation,","venue":null,"work_id":null,"year":2021},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":24,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:39.740716Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:88e29202644d6ea7b94873f0355ab8cf4968b9109d2b724007733c4f43b7e458","observation_id":"8303214b-6a3c-41d4-b4a1-dac35fa685d2","resolution":{"observed_at":"2026-08-01T22:23:39.740716Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2004.12816","last_updated":"2020-04-23T22:36:05Z","snapshot_observed_at":"2026-07-31T00:36:11.204598Z","submitted_at":"2020-04-23T22:36:05Z","title":"Zakharov-Ito equation and Generalized Heisenberg ferromagnet-type equation: equivalence and related geometric curve flows","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2004.12816","snapshot_observed_at":"2026-08-01T22:23:39.829962Z","title":"LLVM: a compilation framework for lifelong program analysis & transformation,","venue":null,"work_id":null,"year":2004},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":25,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:39.829962Z"},"links":{"cited_paper":"/paper/2004.12816","citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:731273913d7d757f7459897bcc92f11c0da2584945d288b892b75cb17a641c3c","observation_id":"05a80759-5e82-4e71-b16e-2a4029e2823c","resolution":{"observed_at":"2026-08-01T22:23:39.829962Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T22:23:39.891598Z","title":"Reusability is FIRRTL ground: Hardware con - struction languages, compiler frameworks, and transformations,","venue":null,"work_id":null,"year":2017},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":26,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:39.891598Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:a379ab3ccac1f26d5bb084922b6f6a606bff19cf5897869925e9880e8dc175ed","observation_id":"68a2af08-116e-4554-b3f0-e797fb043f60","resolution":{"observed_at":"2026-08-01T22:23:39.891598Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T22:23:39.951818Z","title":"LLHD: a multi- level intermediate representation for hardware description languages,","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":27,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:39.951818Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:954ce0432c7ef0118fcab6ef502021ccf4139013357a80a4bfcce9004d824fe0","observation_id":"8f42563e-2d0e-46d7-ad12-d0477c1fe81e","resolution":{"observed_at":"2026-08-01T22:23:39.951818Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T22:23:40.022354Z","title":"IEEE Standard for Standard Delay Format (SDF) for the Electronic Design Process","venue":null,"work_id":null,"year":2026},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":28,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:40.022354Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:72a1ae4342b8318a7f67cf6bd840a0b7f699baca973193745855477387917ff1","observation_id":"a834d7c5-0b09-43ca-b299-2d4ea5eee97d","resolution":{"observed_at":"2026-08-01T22:23:40.022354Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T22:23:40.089031Z","title":"AMASIVE: An Adapt - able and Modular Autonomous Side-Channel Vulnerability Evaluation Framework,","venue":null,"work_id":null,"year":2013},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":29,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:40.089031Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:a69c232eaf4981e67d0283095276565d1dd9da430141da8add7709f61378d19c","observation_id":"e59257cf-8e41-4027-aa6a-5dc08cda0c06","resolution":{"observed_at":"2026-08-01T22:23:40.089031Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T22:23:40.199252Z","title":"RTL-PSC: Automated Power Side-Channel Leakage Assessment at Register-Transfer Level,","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":30,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:40.199252Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:91f63e600065f1ede230c63db850d6911c72af2111663793dcf3b3712bf2cfad","observation_id":"298a929a-1dfe-4a41-980f-8be6d62adaf3","resolution":{"observed_at":"2026-08-01T22:23:40.199252Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T22:23:40.248195Z","title":"SoK: Design Tools for Side-Channel-Aware Implementations,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":31,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:40.248195Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:2366e65bac860a26bf07942d44b872020ab5f6157f837e460ce7d10321202a39","observation_id":"b680b4c6-6b01-4741-8d7f-42b405a0d0f0","resolution":{"observed_at":"2026-08-01T22:23:40.248195Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T22:23:40.309442Z","title":"YosysHQ/picorv32","venue":null,"work_id":null,"year":2026},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":32,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:40.309442Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:569d09a41a6ca94917c38486ecd9562658142d1b3eb22d170ecf2431b273f1d8","observation_id":"0ee1d85f-3a58-4008-996f-fc9b199727d1","resolution":{"observed_at":"2026-08-01T22:23:40.309442Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T22:23:40.387267Z","title":"A Very Compact","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":33,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:40.387267Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:3ff30bb1633f7fc466d2b2d62f05dcb7348129334bf1eb37e4219375c92f90b3","observation_id":"fedc8ab7-d5fc-4525-bf45-d688f7a50b47","resolution":{"observed_at":"2026-08-01T22:23:40.387267Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T22:23:40.463438Z","title":"Cryptographic IP cores","venue":null,"work_id":null,"year":null},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":34,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:40.463438Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:f20c312e7926a634d2392fb04f7d6d7fb81996e606726c347bafffee906cc354","observation_id":"8e8db135-b3cd-4bb3-99fa-b4db5a3b839a","resolution":{"observed_at":"2026-08-01T22:23:40.463438Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T22:23:40.533407Z","title":"FORTIFY: Analytical Pre- Silicon Side-Channel Characterization of Digital Designs,","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":35,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:40.533407Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:edbfe21dc71c82cdfb4ee4eee28941af6bb6677dc4beac95313a38b24c0c376d","observation_id":"854d8249-694d-4126-b718-7be178257581","resolution":{"observed_at":"2026-08-01T22:23:40.533407Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1007/s00145-010-9084-8","metadata_source":"openalex","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":"Mutual Information Analysis: a Comprehensive Study,","venue":"Journal of Cryptology","work_id":"968f31bb-47f7-49fc-ac34-a14aa0fa3b43","year":2011},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":36,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:40.608907Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:0ab41db50ad475f33f5467c9a3f6e4c28faa11093edbd861ee0a62fc3ac08c0c","observation_id":"97b82145-38e1-4604-9778-a583d6f8c29d","resolution":{"observed_at":"2026-08-01T22:28:33.159786Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-09T06:31:02.800959+00:00","source":"crossref"},{"observed_at":"2026-08-09T06:30:57.326959+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1007/978-3-642-42001-6_12","metadata_source":"openalex","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-05T02:28:24.338817Z","title":null,"venue":"Lecture notes in computer science","work_id":"178c8405-88a6-4328-804c-06c6fd745626","year":null},"citing_paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis","version":1},"reference_index":165,"source":"pdf_text","source_observed_at":"2026-08-01T22:23:40.145940Z"},"links":{"citing_paper":"/paper/2607.15782"},"observation_digest":"sha256:6a9af8cf501efe859afb47dde985884316af55a0f129bd96b0b9513d089a33e7","observation_id":"5f80cceb-b542-4577-a2b6-bf8ff1a4bca5","resolution":{"observed_at":"2026-08-01T22:28:33.303137Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-09T06:31:02.800959+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-09T06:31:02.800959+00:00","source":"crossref"},{"observed_at":"2026-08-09T06:30:57.326959+00:00","source":"retraction_watch"}],"state":"measured"}}],"paper":{"arxiv_id":"2607.15782","last_updated":"2026-07-17T09:35:49Z","latest_version":1,"primary_category":"cs.CR","snapshot_observed_at":"2026-08-03T08:10:54.580672Z","submitted_at":"2026-07-17T09:35:49Z","title":"Vogls: a Fast Interactive Full-timing Simulator for Pre-silicon Power Side-Channel Analysis"},"reference_resolution":{"displayed":37,"state_counts":{"malformed_identifier":2,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":29,"verified_exact":6,"verified_fuzzy":0},"total_outbound_references":37},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-09T06:31:02.800959+00:00","source":"crossref"},{"observed_at":"2026-08-09T06:30:57.326959+00:00","source":"retraction_watch"}],"thesis":"As of 9 August 2026, this Paper Citation Record lists 37 of 37 outbound references and 0 inbound Pith citation observations for arXiv:2607.15782."}