{"as_of":"2026-08-23T04:13:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:c939f5daa1d036760d076ed59ba05f1198d2f29155c376c208480d84e1f7bfa8","coverage":[{"denominator":30,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":30,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-01T15:53:45.442161Z","state":"measured"},{"denominator":30,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":30,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-22T06:32:14.747728+00:00","state":"measured"},{"denominator":0,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"cited_works","source_observed_at":null,"state":"measured"}],"external_citation_measurements":[],"inbound":[],"links":{"evidence":"/evidence","html":"/paper/2607.18149/citation-record","integrity":"/paper/2607.18149/integrity","json":"/paper/2607.18149/citation-record.json","paper":"/paper/2607.18149"},"outbound":[{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T15:53:42.832292Z","title":"Deep Learning Approaches for EEG-Motor Imagery-Based BCIs: Current Models, Generalization Challenges, and Emerging Trends","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2607.18149","last_updated":"2026-07-20T16:49:30Z","snapshot_observed_at":"2026-08-08T02:00:41.165521Z","submitted_at":"2026-07-20T16:49:30Z","title":"Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-01T15:53:42.832292Z"},"links":{"citing_paper":"/paper/2607.18149"},"observation_digest":"sha256:523ad02e9976834db86e1d40e110b8abedfa432b554de28591df9b097d63d4e0","observation_id":"d39b1827-6137-4de7-a758-887eaae71b07","resolution":{"observed_at":"2026-08-01T15:53:42.832292Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T15:53:43.002201Z","title":"A Simple Review of EEG Foundation Models: Datasets, Advancements and Future Perspectives","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2607.18149","last_updated":"2026-07-20T16:49:30Z","snapshot_observed_at":"2026-08-08T02:00:41.165521Z","submitted_at":"2026-07-20T16:49:30Z","title":"Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices","version":1},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-01T15:53:43.002201Z"},"links":{"citing_paper":"/paper/2607.18149"},"observation_digest":"sha256:4a45008ad89c6abedd41de20e1edc6c2da015a2f5cd3a0014111a7b7915501c8","observation_id":"166e403d-adf4-455e-8fd6-f8641b9eaeed","resolution":{"observed_at":"2026-08-01T15:53:43.002201Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T15:53:43.063792Z","title":"Challenges, Limitations, and Future Directions in EEG-Driven Image Classification using Machine Learning","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2607.18149","last_updated":"2026-07-20T16:49:30Z","snapshot_observed_at":"2026-08-08T02:00:41.165521Z","submitted_at":"2026-07-20T16:49:30Z","title":"Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices","version":1},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-01T15:53:43.063792Z"},"links":{"citing_paper":"/paper/2607.18149"},"observation_digest":"sha256:80467d1591cd3c0c798e6de2b4a8d206833310578e014b3fe00a6abb73fc3c4b","observation_id":"f8983724-a092-43ee-a476-5af4094f8a68","resolution":{"observed_at":"2026-08-01T15:53:43.063792Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T15:53:43.172965Z","title":"Eeg founda- tion models: A critical review of current progress and future directions","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2607.18149","last_updated":"2026-07-20T16:49:30Z","snapshot_observed_at":"2026-08-08T02:00:41.165521Z","submitted_at":"2026-07-20T16:49:30Z","title":"Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices","version":1},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-01T15:53:43.172965Z"},"links":{"citing_paper":"/paper/2607.18149"},"observation_digest":"sha256:eaf8e66c8422176160352bca2b2441fa9133261cd334f1fe1af9b2a4c3db5aeb","observation_id":"ac4953d3-2026-4226-8819-1f0c94406d37","resolution":{"observed_at":"2026-08-01T15:53:43.172965Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T15:53:43.249710Z","title":"A Comprehensive Survey on Wearable Computing for Mental and Physical Health Monitoring","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2607.18149","last_updated":"2026-07-20T16:49:30Z","snapshot_observed_at":"2026-08-08T02:00:41.165521Z","submitted_at":"2026-07-20T16:49:30Z","title":"Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices","version":1},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-08-01T15:53:43.249710Z"},"links":{"citing_paper":"/paper/2607.18149"},"observation_digest":"sha256:1be08b439a67d423dd1a6ed91b3205e380e96b3c0346aa67806042527a56c9c5","observation_id":"4958cb36-6e2c-4c99-9567-d7df18dbd119","resolution":{"observed_at":"2026-08-01T15:53:43.249710Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T15:53:43.374267Z","title":"A low-latency neural inference framework for real-time handwriting recogni- tion from EEG signals on an edge device: O. Sen et al","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2607.18149","last_updated":"2026-07-20T16:49:30Z","snapshot_observed_at":"2026-08-08T02:00:41.165521Z","submitted_at":"2026-07-20T16:49:30Z","title":"Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices","version":1},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-01T15:53:43.374267Z"},"links":{"citing_paper":"/paper/2607.18149"},"observation_digest":"sha256:f25f51dcfef25ce633f90dd945935e8026b79db02f71fbc2a8fdceef7c64b977","observation_id":"b1c5bb81-161d-4e57-b72a-8706609095a4","resolution":{"observed_at":"2026-08-01T15:53:43.374267Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T15:53:43.458370Z","title":"Deep differentiable logic gate networks","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2607.18149","last_updated":"2026-07-20T16:49:30Z","snapshot_observed_at":"2026-08-08T02:00:41.165521Z","submitted_at":"2026-07-20T16:49:30Z","title":"Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-01T15:53:43.458370Z"},"links":{"citing_paper":"/paper/2607.18149"},"observation_digest":"sha256:4145345c3b8582b5a74b45336eb466ffa8d9142255e0c2ff855036035981eb7a","observation_id":"612a6b68-3c50-4f96-ade3-fe086d705470","resolution":{"observed_at":"2026-08-01T15:53:43.458370Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T15:53:43.536216Z","title":"Convolutional differentiable logic gate networks","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2607.18149","last_updated":"2026-07-20T16:49:30Z","snapshot_observed_at":"2026-08-08T02:00:41.165521Z","submitted_at":"2026-07-20T16:49:30Z","title":"Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices","version":1},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-01T15:53:43.536216Z"},"links":{"citing_paper":"/paper/2607.18149"},"observation_digest":"sha256:d1da282fa1509df7fa6b01ce934988a003eeb4797020f35562a8b0ee30102d4e","observation_id":"1ffdcd0a-6e2e-4079-bc6f-0d3f42a6e34a","resolution":{"observed_at":"2026-08-01T15:53:43.536216Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T15:53:43.627439Z","title":"Recurrent deep differentiable logic gate networks","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2607.18149","last_updated":"2026-07-20T16:49:30Z","snapshot_observed_at":"2026-08-08T02:00:41.165521Z","submitted_at":"2026-07-20T16:49:30Z","title":"Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices","version":1},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-01T15:53:43.627439Z"},"links":{"citing_paper":"/paper/2607.18149"},"observation_digest":"sha256:2f728141eecc5967938393ba1bd0a658e6f9b30bbdee6c4ec5c96247dfa33d1d","observation_id":"ef9ec059-0775-4309-8cee-4b91739ee2f8","resolution":{"observed_at":"2026-08-01T15:53:43.627439Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T15:53:43.731320Z","title":"Light Differentiable Logic Gate Networks","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2607.18149","last_updated":"2026-07-20T16:49:30Z","snapshot_observed_at":"2026-08-08T02:00:41.165521Z","submitted_at":"2026-07-20T16:49:30Z","title":"Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-01T15:53:43.731320Z"},"links":{"citing_paper":"/paper/2607.18149"},"observation_digest":"sha256:a8c1dad01e4d5ef5aafa4945e13131375ed04cd89f25e84dc86e9727bbbb4820","observation_id":"8a27a6d2-36a8-4ee1-ac74-83a500a41774","resolution":{"observed_at":"2026-08-01T15:53:43.731320Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T15:53:43.810852Z","title":"Deep learning with convolutional neural networks for EEG decoding and visualization","venue":null,"work_id":null,"year":2017},"citing_paper":{"arxiv_id":"2607.18149","last_updated":"2026-07-20T16:49:30Z","snapshot_observed_at":"2026-08-08T02:00:41.165521Z","submitted_at":"2026-07-20T16:49:30Z","title":"Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices","version":1},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-01T15:53:43.810852Z"},"links":{"citing_paper":"/paper/2607.18149"},"observation_digest":"sha256:1773719512053094f988b10abd4b7a4fe11abc19e556be18cf56d048ab840dbe","observation_id":"15f0ee82-f265-406f-8d07-34526a4964dd","resolution":{"observed_at":"2026-08-01T15:53:43.810852Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T15:53:43.881019Z","title":"EEGNet: a compact convolutional neural network for EEG-based brain–computer inter- faces","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2607.18149","last_updated":"2026-07-20T16:49:30Z","snapshot_observed_at":"2026-08-08T02:00:41.165521Z","submitted_at":"2026-07-20T16:49:30Z","title":"Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices","version":1},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-01T15:53:43.881019Z"},"links":{"citing_paper":"/paper/2607.18149"},"observation_digest":"sha256:5702b52dde1dfed97baade0ad0078cfec594ab56acbe0ad075585d77c3faa999","observation_id":"7ae1d7e5-dd14-4eb5-9a0d-ad4a1614a6b1","resolution":{"observed_at":"2026-08-01T15:53:43.881019Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T15:53:43.937631Z","title":"EEG conformer: Convolutional transformer for EEG decoding and visualization","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2607.18149","last_updated":"2026-07-20T16:49:30Z","snapshot_observed_at":"2026-08-08T02:00:41.165521Z","submitted_at":"2026-07-20T16:49:30Z","title":"Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices","version":1},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-01T15:53:43.937631Z"},"links":{"citing_paper":"/paper/2607.18149"},"observation_digest":"sha256:8ba66b1dbb1eab7618f36526f86e477d8c30913e2e74c644f9f45e623c30dea4","observation_id":"e737d1b8-4b94-4a6e-86fc-27f983a25f13","resolution":{"observed_at":"2026-08-01T15:53:43.937631Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2405.18765","last_updated":"2024-05-29T05:08:16Z","snapshot_observed_at":"2026-08-20T07:01:07.998040Z","submitted_at":"2024-05-29T05:08:16Z","title":"Large Brain Model for Learning Generic Representations with Tremendous EEG Data in BCI","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2405.18765","snapshot_observed_at":"2026-08-01T15:53:44.031741Z","title":"Large brain model for learning generic representa- tions with tremendous EEG data in BCI","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2607.18149","last_updated":"2026-07-20T16:49:30Z","snapshot_observed_at":"2026-08-08T02:00:41.165521Z","submitted_at":"2026-07-20T16:49:30Z","title":"Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices","version":1},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-01T15:53:44.031741Z"},"links":{"cited_paper":"/paper/2405.18765","citing_paper":"/paper/2607.18149"},"observation_digest":"sha256:768a57a85c3d9b7c7e2b8aed49f5bd27e78a25cdbe01496d7643b951b9c68afc","observation_id":"915b3628-c33c-4123-be13-a28f866c1ff1","resolution":{"observed_at":"2026-08-01T15:53:44.031741Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T15:53:44.168581Z","title":"Biot: Biosignal transformer for cross-data learning in the wild","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2607.18149","last_updated":"2026-07-20T16:49:30Z","snapshot_observed_at":"2026-08-08T02:00:41.165521Z","submitted_at":"2026-07-20T16:49:30Z","title":"Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices","version":1},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-08-01T15:53:44.168581Z"},"links":{"citing_paper":"/paper/2607.18149"},"observation_digest":"sha256:64cc1f88a6c33d8ea4e7e92dd7863e79d13741ca6e08e1185195aefe1f8ceaf1","observation_id":"fb5d140f-59ab-43e1-a397-56283f806b0b","resolution":{"observed_at":"2026-08-01T15:53:44.168581Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T15:53:44.247675Z","title":"DeeperBrain: A Neuro-Grounded EEG Foundation Model Towards Universal BCI","venue":null,"work_id":null,"year":2026},"citing_paper":{"arxiv_id":"2607.18149","last_updated":"2026-07-20T16:49:30Z","snapshot_observed_at":"2026-08-08T02:00:41.165521Z","submitted_at":"2026-07-20T16:49:30Z","title":"Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices","version":1},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-01T15:53:44.247675Z"},"links":{"citing_paper":"/paper/2607.18149"},"observation_digest":"sha256:ed93bd3140b0b8931bcad60f9e4e90b2f3e4a6d1240a360dcec52c2e22f11ce7","observation_id":"44341292-bb69-4a72-aef4-b0bc739d5bf8","resolution":{"observed_at":"2026-08-01T15:53:44.247675Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T15:53:44.339613Z","title":"LUNA: Efficient and topology-agnostic foundation model for EEG signal analysis","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2607.18149","last_updated":"2026-07-20T16:49:30Z","snapshot_observed_at":"2026-08-08T02:00:41.165521Z","submitted_at":"2026-07-20T16:49:30Z","title":"Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-01T15:53:44.339613Z"},"links":{"citing_paper":"/paper/2607.18149"},"observation_digest":"sha256:c52d09c0dc1d4dde56f2134145fdf4ce823ff306266c728f1607983cb0d2b51e","observation_id":"1bb94545-1be5-4583-9498-cbc8751e11d2","resolution":{"observed_at":"2026-08-01T15:53:44.339613Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T15:53:44.395294Z","title":"FEMBA: Efficient and Scalable EEGAnalysiswithaBidirectionalMambaFoundationModel","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2607.18149","last_updated":"2026-07-20T16:49:30Z","snapshot_observed_at":"2026-08-08T02:00:41.165521Z","submitted_at":"2026-07-20T16:49:30Z","title":"Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices","version":1},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-01T15:53:44.395294Z"},"links":{"citing_paper":"/paper/2607.18149"},"observation_digest":"sha256:61b0e415c7d34bf30055cb3e0571f2dcceef735f7d22c67c38f3406bab5d18d1","observation_id":"d0a89f7c-dbd7-4452-8244-f08ba10863d2","resolution":{"observed_at":"2026-08-01T15:53:44.395294Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"1503.02531","last_updated":"2015-03-09T15:44:49Z","snapshot_observed_at":"2026-08-16T18:00:58.008096Z","submitted_at":"2015-03-09T15:44:49Z","title":"Distilling the Knowledge in a Neural Network","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"1503.02531","snapshot_observed_at":"2026-08-01T15:53:44.479074Z","title":"Distilling the knowledge in a neural network","venue":null,"work_id":null,"year":2015},"citing_paper":{"arxiv_id":"2607.18149","last_updated":"2026-07-20T16:49:30Z","snapshot_observed_at":"2026-08-08T02:00:41.165521Z","submitted_at":"2026-07-20T16:49:30Z","title":"Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices","version":1},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-08-01T15:53:44.479074Z"},"links":{"cited_paper":"/paper/1503.02531","citing_paper":"/paper/2607.18149"},"observation_digest":"sha256:3ca47ad27c01b8ec382b2152345cbea70fe106607d8093d97d8e53d4c95e3e7b","observation_id":"c12d1e9b-c931-4551-8db6-b9400f38f0e8","resolution":{"observed_at":"2026-08-01T15:53:44.479074Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"1510.00149","last_updated":"2016-02-15T06:25:40Z","snapshot_observed_at":"2026-08-04T16:59:47.843960Z","submitted_at":"2015-10-01T09:03:44Z","title":"Deep Compression: Compressing Deep Neural Networks with Pruning, Trained Quantization and Huffman Coding","version":5},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"1510.00149","snapshot_observed_at":"2026-08-01T15:53:44.582407Z","title":"Deep compression: Compressing deep neural networks with pruning, trained quantization and huffman coding","venue":null,"work_id":null,"year":2015},"citing_paper":{"arxiv_id":"2607.18149","last_updated":"2026-07-20T16:49:30Z","snapshot_observed_at":"2026-08-08T02:00:41.165521Z","submitted_at":"2026-07-20T16:49:30Z","title":"Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices","version":1},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-08-01T15:53:44.582407Z"},"links":{"cited_paper":"/paper/1510.00149","citing_paper":"/paper/2607.18149"},"observation_digest":"sha256:a3d033bf0762fda6afe9709b133ac1e39c6b90b731e6e27c4c615ba3bb301338","observation_id":"83100f66-eb51-4cb0-bc9d-3dc7d7b64f0a","resolution":{"observed_at":"2026-08-01T15:53:44.582407Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"1602.02830","last_updated":"2016-03-17T14:54:25Z","snapshot_observed_at":"2026-08-15T07:00:41.403404Z","submitted_at":"2016-02-09T01:01:59Z","title":"Binarized Neural Networks: Training Deep Neural Networks with Weights and Activations Constrained to +1 or -1","version":3},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"1602.02830","snapshot_observed_at":"2026-08-01T15:53:44.708622Z","title":"Binarized neural net- works: Training deep neural networks with weights and activations constrained to+ 1 or-1","venue":null,"work_id":null,"year":2016},"citing_paper":{"arxiv_id":"2607.18149","last_updated":"2026-07-20T16:49:30Z","snapshot_observed_at":"2026-08-08T02:00:41.165521Z","submitted_at":"2026-07-20T16:49:30Z","title":"Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices","version":1},"reference_index":21,"source":"pdf_text","source_observed_at":"2026-08-01T15:53:44.708622Z"},"links":{"cited_paper":"/paper/1602.02830","citing_paper":"/paper/2607.18149"},"observation_digest":"sha256:585c54468edd05466d5c92af99f973cadf2934841191379c73fac1ce9c3ffc34","observation_id":"cea5fbf7-5d02-4cc8-aa45-b2ac79ab7e4f","resolution":{"observed_at":"2026-08-01T15:53:44.708622Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T15:53:44.786151Z","title":"MuBiNN: Multi-level bina- rized recurrent neural network for EEG signal classification","venue":null,"work_id":null,"year":2020},"citing_paper":{"arxiv_id":"2607.18149","last_updated":"2026-07-20T16:49:30Z","snapshot_observed_at":"2026-08-08T02:00:41.165521Z","submitted_at":"2026-07-20T16:49:30Z","title":"Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices","version":1},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-01T15:53:44.786151Z"},"links":{"citing_paper":"/paper/2607.18149"},"observation_digest":"sha256:3236c1403da586d5b931302a2acb5e6a38e57b105a574f8c0c2f1914925e09e8","observation_id":"26696884-2707-49e0-9f96-f33db54f64c6","resolution":{"observed_at":"2026-08-01T15:53:44.786151Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T15:53:44.865736Z","title":"A dataset of scalp EEG recordings of Alzheimer’s disease, frontotemporal dementia and healthy subjects from routine EEG","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2607.18149","last_updated":"2026-07-20T16:49:30Z","snapshot_observed_at":"2026-08-08T02:00:41.165521Z","submitted_at":"2026-07-20T16:49:30Z","title":"Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices","version":1},"reference_index":23,"source":"pdf_text","source_observed_at":"2026-08-01T15:53:44.865736Z"},"links":{"citing_paper":"/paper/2607.18149"},"observation_digest":"sha256:90d826d0565776d388e81830ebedc5c44bb0f9a085b57feda3939b0dee8b0581","observation_id":"98f893be-03c0-42a8-ac31-1745b0205745","resolution":{"observed_at":"2026-08-01T15:53:44.865736Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T15:53:44.961330Z","title":"Investigating Critical Frequency Bands and Channels for EEG- based Emotion Recognition with Deep Neural Networks","venue":null,"work_id":null,"year":2015},"citing_paper":{"arxiv_id":"2607.18149","last_updated":"2026-07-20T16:49:30Z","snapshot_observed_at":"2026-08-08T02:00:41.165521Z","submitted_at":"2026-07-20T16:49:30Z","title":"Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices","version":1},"reference_index":24,"source":"pdf_text","source_observed_at":"2026-08-01T15:53:44.961330Z"},"links":{"citing_paper":"/paper/2607.18149"},"observation_digest":"sha256:a3c51a2fc012361a6389f80ca0a5c7df4e1bf61a6044c418b6210c5d5c6741a3","observation_id":"19198945-d4d7-45c0-ba6b-b7ea1d233b96","resolution":{"observed_at":"2026-08-01T15:53:44.961330Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T15:53:45.032879Z","title":"Identifying similarities and differences in emotion recognition with EEG and eye movements among Chinese, German, and French People","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2607.18149","last_updated":"2026-07-20T16:49:30Z","snapshot_observed_at":"2026-08-08T02:00:41.165521Z","submitted_at":"2026-07-20T16:49:30Z","title":"Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices","version":1},"reference_index":25,"source":"pdf_text","source_observed_at":"2026-08-01T15:53:45.032879Z"},"links":{"citing_paper":"/paper/2607.18149"},"observation_digest":"sha256:93b4f70a18eb5c96bf8297ab91110474950536aebf83296782d9525885c20d36","observation_id":"8be3091d-3a52-4cd7-85c4-335503ff629f","resolution":{"observed_at":"2026-08-01T15:53:45.032879Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T15:53:45.134561Z","title":"A review of classification algorithms for EEG-based brain–computer interfaces: a 10 year update","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2607.18149","last_updated":"2026-07-20T16:49:30Z","snapshot_observed_at":"2026-08-08T02:00:41.165521Z","submitted_at":"2026-07-20T16:49:30Z","title":"Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices","version":1},"reference_index":26,"source":"pdf_text","source_observed_at":"2026-08-01T15:53:45.134561Z"},"links":{"citing_paper":"/paper/2607.18149"},"observation_digest":"sha256:b1125cbe379f8a0b1ead9c2e7ffed5db907d3fa2d8c4a1c4437ba203c0c3d856","observation_id":"b2bec26e-141e-4136-96b7-172441d994e2","resolution":{"observed_at":"2026-08-01T15:53:45.134561Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T15:53:45.189890Z","title":"Thermometer encoding: One hot way to resist adversarial examples","venue":null,"work_id":null,"year":2018},"citing_paper":{"arxiv_id":"2607.18149","last_updated":"2026-07-20T16:49:30Z","snapshot_observed_at":"2026-08-08T02:00:41.165521Z","submitted_at":"2026-07-20T16:49:30Z","title":"Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices","version":1},"reference_index":27,"source":"pdf_text","source_observed_at":"2026-08-01T15:53:45.189890Z"},"links":{"citing_paper":"/paper/2607.18149"},"observation_digest":"sha256:7dc324a795b88793704ed21bfbdd4287d51f657e1031d78ab5ba9f3118dc836c","observation_id":"9a2a0af6-045e-40ed-a17e-c6fbc3e965a0","resolution":{"observed_at":"2026-08-01T15:53:45.189890Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T15:53:45.279189Z","title":"Post training 4-bit quantization of convolutional networks for rapid-deployment","venue":null,"work_id":null,"year":2019},"citing_paper":{"arxiv_id":"2607.18149","last_updated":"2026-07-20T16:49:30Z","snapshot_observed_at":"2026-08-08T02:00:41.165521Z","submitted_at":"2026-07-20T16:49:30Z","title":"Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices","version":1},"reference_index":28,"source":"pdf_text","source_observed_at":"2026-08-01T15:53:45.279189Z"},"links":{"citing_paper":"/paper/2607.18149"},"observation_digest":"sha256:82836203ad14d160b0bdde64611868aa9748ca447ab2221131a0754fcdae4e39","observation_id":"514de890-8625-48d4-9e90-92a240993664","resolution":{"observed_at":"2026-08-01T15:53:45.279189Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-01T15:53:45.350284Z","title":"3575392- r2","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2607.18149","last_updated":"2026-07-20T16:49:30Z","snapshot_observed_at":"2026-08-08T02:00:41.165521Z","submitted_at":"2026-07-20T16:49:30Z","title":"Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices","version":1},"reference_index":29,"source":"pdf_text","source_observed_at":"2026-08-01T15:53:45.350284Z"},"links":{"citing_paper":"/paper/2607.18149"},"observation_digest":"sha256:d4f8ab8db6f4743e9d11826e8df69659f45edd26a998c3418b22a8f568b1c764","observation_id":"dcc6b29b-d150-4e4f-beb7-042b7b6322ce","resolution":{"observed_at":"2026-08-01T15:53:45.350284Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2301.11110","last_updated":"2023-01-23T11:46:59Z","snapshot_observed_at":"2026-08-16T16:00:46.401372Z","submitted_at":"2023-01-23T11:46:59Z","title":"Device JNEEG to convert Jetson Nano to brain-Computer interfaces. Short report","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2301.11110","snapshot_observed_at":"2026-08-01T15:53:45.442161Z","title":"Device JNEEG to convert Jetson Nano to brain-Computer interfaces. Short report","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2607.18149","last_updated":"2026-07-20T16:49:30Z","snapshot_observed_at":"2026-08-08T02:00:41.165521Z","submitted_at":"2026-07-20T16:49:30Z","title":"Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices","version":1},"reference_index":30,"source":"pdf_text","source_observed_at":"2026-08-01T15:53:45.442161Z"},"links":{"cited_paper":"/paper/2301.11110","citing_paper":"/paper/2607.18149"},"observation_digest":"sha256:7159298da0d35761fb27a722d7f9c0f100c4341986fd4c5cd740794f49760c02","observation_id":"bfab8966-8964-42a3-b5d3-be49c15eacb3","resolution":{"observed_at":"2026-08-01T15:53:45.442161Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}}],"paper":{"arxiv_id":"2607.18149","last_updated":"2026-07-20T16:49:30Z","latest_version":1,"primary_category":"cs.LG","snapshot_observed_at":"2026-08-08T02:00:41.165521Z","submitted_at":"2026-07-20T16:49:30Z","title":"Differentiable Logic Gate Networks for Low-Latency EEG Classification on Edge Devices"},"reference_resolution":{"displayed":30,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":30,"verified_exact":0,"verified_fuzzy":0},"total_outbound_references":30},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-22T06:32:14.747728+00:00","source":"crossref"},{"observed_at":"2026-08-22T06:32:06.552537+00:00","source":"retraction_watch"}],"thesis":"As of 23 August 2026, this Paper Citation Record lists 30 of 30 outbound references and 0 inbound Pith citation observations for arXiv:2607.18149."}