{"as_of":"2026-08-13T13:05:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:f0ba5d51eac077debbc58ed5b4544d4eaa01ef882990200e3d11f5f44c85c7a8","coverage":[{"denominator":89,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":89,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-08T00:12:40.544529Z","state":"measured"},{"denominator":89,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":89,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-13T06:32:02.005865+00:00","state":"measured"},{"denominator":0,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"cited_works","source_observed_at":null,"state":"measured"}],"external_citation_measurements":[],"inbound":[],"links":{"evidence":"/evidence","html":"/paper/2608.04247/citation-record","integrity":"/paper/2608.04247/integrity","json":"/paper/2608.04247/citation-record.json","paper":"/paper/2608.04247"},"outbound":[{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.255294Z","title":"https://developer.arm.com/documentation/ddi0598/ latest/","venue":null,"work_id":null,"year":null},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.255294Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:396c077b75ddd2bf01634060d49cf6d56e0b91db15147896aace8533088e4180","observation_id":"3b8862a1-2dae-4a6c-858c-342303e17491","resolution":{"observed_at":"2026-08-08T00:12:40.255294Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.259882Z","title":"https://www.intel.com/content/www/us/en/architecture-and-technology/ resource-director-technology.html","venue":null,"work_id":null,"year":null},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.259882Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:ee6edcf1a8298aa741a5dbde46ee9cea317b9e60f5f884d729af6a2b6ad3b15a","observation_id":"2c212d6a-63bd-423d-879f-a325acd4c9c2","resolution":{"observed_at":"2026-08-08T00:12:40.259882Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.264069Z","title":"AXI performance monitor, Zynq UltraScale+ Device Tech- nical Reference Manual (UG1085)","venue":null,"work_id":null,"year":null},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.264069Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:49c7d808e8f2d6ac98001c7fae84ba429c589d6a8dbf974f0b3820922ee4836e","observation_id":"b7398d72-fb52-4189-9644-e8d9c6a9f86b","resolution":{"observed_at":"2026-08-08T00:12:40.264069Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.267594Z","title":"Kanev et al","venue":null,"work_id":null,"year":2015},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.267594Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:ac55471d7eb57f5a30df196324fe42b1307e681c80ebbfadfe1c5672bd357242","observation_id":"6634bb61-d281-48b9-b8e0-f390d9e48cf4","resolution":{"observed_at":"2026-08-08T00:12:40.267594Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.271477Z","title":"Adl-Tabatabai et al","venue":null,"work_id":null,"year":2004},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.271477Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:12e42f67465342fe6a839c860be7cd5eea11f301252e870e44ffc450fb9c39ab","observation_id":"2c688096-be20-40d2-b273-0a783fdf4be0","resolution":{"observed_at":"2026-08-08T00:12:40.271477Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.275020Z","title":"Oh et al","venue":null,"work_id":null,"year":2022},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.275020Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:964cfd34ee5a15e2eda8aac6a86eb775d08be82be35a3a0d5cd7c26e3a6b4f0a","observation_id":"ff27c6fe-5fc4-4a95-b0d2-8ee52efa861a","resolution":{"observed_at":"2026-08-08T00:12:40.275020Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.279034Z","title":"Yun et al","venue":null,"work_id":null,"year":2013},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.279034Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:91eebb77c2024023a6af0816f6a2d3a11c73b0180711e729e3deef5aacaf984b","observation_id":"bfdbb172-8a0e-43ee-970e-6a8de402898f","resolution":{"observed_at":"2026-08-08T00:12:40.279034Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"1903.01314","last_updated":"2019-03-04T15:48:00Z","snapshot_observed_at":"2026-07-06T07:36:53.294091Z","submitted_at":"2019-03-04T15:48:00Z","title":"Denial-of-Service Attacks on Shared Cache in Multicore: Analysis and Prevention","version":1},"cited_work":{"arxiv_id":"1903.01314","doi":null,"metadata_source":"pith","pith_arxiv_id":"1903.01314","snapshot_observed_at":"2026-08-08T00:12:40.701186Z","title":"Denial-of-Service Attacks on Shared Cache in Multicore: Analysis and Prevention","venue":"cs.AR","work_id":"267282f1-522f-4a52-8d74-e3c5986b9b59","year":2019},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.282856Z"},"links":{"cited_paper":"/paper/1903.01314","citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:9f95e80646a5b73227a49ba120e628aa7df1e84c6664a7a2a05f63dbca513042","observation_id":"f20a04f3-8eca-47d1-b489-6c93c653cc40","resolution":{"observed_at":"2026-08-08T00:12:40.705503Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.287253Z","title":"Dagieu et al","venue":null,"work_id":null,"year":2016},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.287253Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:3beef7f06bf29a96c3722f8226d5ff29b47fcc560c134da98277d8cf6df92819","observation_id":"f5eeec8b-3f91-426c-b848-13452ad94a2b","resolution":{"observed_at":"2026-08-08T00:12:40.287253Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.290621Z","title":"Z ¨upke et al","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.290621Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:9f74eb26a0b27e1078c71f75d9494ebf005b5beca90613a0c30334a933977bff","observation_id":"753c4c63-46d3-40ad-86bd-fbdbb9e877aa","resolution":{"observed_at":"2026-08-08T00:12:40.290621Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.426804Z","title":"Saeed et al","venue":null,"work_id":"8441f7e8-7406-4b53-a6e9-19826700c06c","year":2023},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.293969Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:7a50331685049e4622a32e188460abb5dc49f7a96f048ef4777c82e3b6ccf9d4","observation_id":"2947f102-da20-427a-a60a-de1224935e19","resolution":{"observed_at":"2026-08-08T00:12:41.430008Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.416640Z","title":"Farshchi et al","venue":null,"work_id":"cd84db90-fc1f-465d-b83c-3ba965b74cb0","year":2020},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.297815Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:a9d9965dc1370ee189a9e064df0800290813854c8ae61e3912825315cb8f6aed","observation_id":"a4275472-c22c-4fcd-9cc9-9d8ae088341f","resolution":{"observed_at":"2026-08-08T00:12:41.420759Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.407256Z","title":"Na et al","venue":null,"work_id":"961101bf-bbcd-4e51-bc14-3ee7fed51bdd","year":2021},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.301290Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:a3ddfbb14e2cf011a5c699011444ce89f5d3ec7692ce99566bd4ca95334712c2","observation_id":"b0cd2521-77e7-4ec2-b0e1-cfe062bcd232","resolution":{"observed_at":"2026-08-08T00:12:41.410591Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.397793Z","title":"Barrera et al","venue":null,"work_id":"ada15519-870b-4af2-ad65-5076f7d8be05","year":2022},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.305528Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:56e86cda33850bacdfee6f871dfc642e42428ae9687495b3560070a577acf44d","observation_id":"1ef3b633-beb8-4461-a902-decb6cfd4c92","resolution":{"observed_at":"2026-08-08T00:12:41.401113Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.386701Z","title":"Roy et al","venue":null,"work_id":"e7b91b24-e904-4d8c-960d-4bac7f3c953d","year":2023},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.308773Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:ccab6ced7696c8193a34a641f8186546df93266ab9da4f7e697a77da24eb033e","observation_id":"2dbd76d8-e010-4c7e-924f-1c25ef5294c0","resolution":{"observed_at":"2026-08-08T00:12:41.391018Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.378261Z","title":null,"venue":null,"work_id":"e88665fe-34f7-4ff6-a931-daeb753bf9fe","year":2021},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.311899Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:0cf30636b9e0c619bdca2d8a45b50a9d667de6107adc5cae9b3e9e84e670167f","observation_id":"3fde693e-d4db-45af-a80e-e496d31cf0b3","resolution":{"observed_at":"2026-08-08T00:12:41.381045Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.370010Z","title":"Pradhan et al","venue":null,"work_id":"4d0b9ed1-2194-4308-9154-61b9441a977d","year":2025},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.314998Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:b9600c012c81ccb559388fa7dc9eee5da16ae8c262cfcf73d05c9e739455dd6b","observation_id":"c6dd8c86-6138-4ca4-bacc-bbdab0042364","resolution":{"observed_at":"2026-08-08T00:12:41.372797Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.359280Z","title":"Chen et al","venue":null,"work_id":"d9c9906d-d718-480c-8166-0bdd290f5437","year":2021},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.318122Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:5ef29fdad42d0967e2eb404c76619ba727eb715ee291960b6c2409b35dc4ce83","observation_id":"2a41ce27-6c11-4ab1-af32-66a2538eadd3","resolution":{"observed_at":"2026-08-08T00:12:41.363579Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.349252Z","title":"https://perf.wiki.kernel.org/index.php/Main Page","venue":null,"work_id":"9c87a8ad-23ab-4bd8-95c1-454b66296bd8","year":null},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.321287Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:1cacb4b0ac8bc30c54e34de4fb29c4b80c7ea04dba57117a7200ded22ff57f05","observation_id":"19329927-7fd8-4601-9eff-d6ac08085dfd","resolution":{"observed_at":"2026-08-08T00:12:41.352940Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.339524Z","title":"R ¨ohl et al","venue":null,"work_id":"c0a6df8c-850f-4da4-9fec-f463114961c4","year":2014},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.324683Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:db7666662d98d4802356d979036f4284cefb23a224c46dde231c8bbf3c2bfa23","observation_id":"5ecbb458-f0c7-44e7-80d0-756baf789ecc","resolution":{"observed_at":"2026-08-08T00:12:41.343009Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.330366Z","title":"Lo et al","venue":null,"work_id":"a0d0415a-d3eb-45fa-9982-f60b33facccd","year":2015},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":21,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.328421Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:bdf2fdbc0529f91f8ea693aa8c2a3697d703e50946052f4f1b6b50f865f360da","observation_id":"cabece60-824d-499d-83b7-580a8005f421","resolution":{"observed_at":"2026-08-08T00:12:41.333580Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.319517Z","title":"https:// www.man7.org/linux/man-pages/man1/perf-stat.1.html, 2024","venue":null,"work_id":"0abf7849-a1f6-4853-94c2-039b3b687f7c","year":2024},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":22,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.331510Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:1e46391287bc9b25881e2a1e880367f72ccc496f77aee214885f60da4f24388c","observation_id":"a4b3a375-10b8-4daf-b920-8d98ef6a9dad","resolution":{"observed_at":"2026-08-08T00:12:41.323763Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.309754Z","title":"Gottschall et al","venue":null,"work_id":"b7c92855-fa81-41e3-bbf5-a410c9ed66a2","year":2021},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":23,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.334608Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:befa0037519215aa7f8ebda9075a4ed5894b810e0b39abe329f1dce18baebeae","observation_id":"50824b61-39b0-4a8f-b077-48600beac5f6","resolution":{"observed_at":"2026-08-08T00:12:41.313167Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.299437Z","title":"Yi et al","venue":null,"work_id":"3dfb7808-825a-43c3-b84b-7b98843195a6","year":2020},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":24,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.337149Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:9810ef781a8e10bbc19441c864aab0ce1f11300039df344d1aada3c798f9db11","observation_id":"26fe2f87-ede5-439a-a809-4d83e48b6264","resolution":{"observed_at":"2026-08-08T00:12:41.302826Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.288145Z","title":"Das et al","venue":null,"work_id":"a833760c-7ee2-4ab9-b40d-1c91fd2bdce2","year":2019},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":25,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.339734Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:880b87d534091cc480e065de12d2ce7616a50e6e216b8e29425f5cb69de8ed59","observation_id":"d41f2443-fbec-422d-905f-fc941885e736","resolution":{"observed_at":"2026-08-08T00:12:41.292396Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.279398Z","title":"https://developer.arm.com/Architectures/ CoreSight%20Architecture","venue":null,"work_id":"4564d39b-9a91-4610-90c5-f4663f05a9cd","year":null},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":26,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.342267Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:e82c8f87f20407fa9785bc6cefd5d6d8519a24dcaa735364e6c49f2d82df3564","observation_id":"3134d82b-e070-4b69-adfe-1db8316ddf48","resolution":{"observed_at":"2026-08-08T00:12:41.282409Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.270747Z","title":"Intel® 64 and IA-32 Architectures Soft- ware Developer’s Manual, V olume 3 (3A, 3B, 3C & 3D): Sys- tem Programming Guide","venue":null,"work_id":"403c2b8c-48ea-4f13-a47a-927803d7e150","year":2024},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":27,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.345132Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:f267d0de93443c11d3690d75b78b5f21b2158381fb0820bc5967b2ee05417cce","observation_id":"b8e93965-673d-4d13-b713-1e0b23715542","resolution":{"observed_at":"2026-08-08T00:12:41.273862Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.260719Z","title":"Arm Architecture Reference Manual Supplement: Sta- tistical profiling extension, for Armv8-A","venue":null,"work_id":"f4b27403-3d56-4845-a53a-3420b71b06f6","year":2017},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":28,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.347846Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:fc2ab2697261dc16b1f05aaa99cabf3c1ca715e7b02db5a79fc882e7bede390a","observation_id":"f23a022e-5ef6-413a-959a-234544790499","resolution":{"observed_at":"2026-08-08T00:12:41.264481Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.251137Z","title":"https://developer","venue":null,"work_id":"205e78e1-587c-4c05-886f-723175938f5e","year":2017},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":29,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.351047Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:07893c1cbad3a6f6c54d38126359fb17804bede789241348edfd964286b94886","observation_id":"1a122539-7a23-4a67-9446-c4668d699b60","resolution":{"observed_at":"2026-08-08T00:12:41.254451Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.241664Z","title":"Waterman et al.The RISC-V Instruction Set Manual, Volume I: User-Level ISA, Document Version 20191213","venue":null,"work_id":"69e6c066-ca9e-47f9-9ffb-d9d0fdf95301","year":2019},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":30,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.353685Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:6b152b30748c8c6e7644aad304624980602de7be4eb7ba620241fc9046ccb557","observation_id":"4df733f5-e8f1-4d3d-9ecc-533d73427ab0","resolution":{"observed_at":"2026-08-08T00:12:41.245104Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.230572Z","title":"Zicntr” and “Zihpm","venue":null,"work_id":"1c213fdd-643b-45d5-a5f5-10a666849a3e","year":2023},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":31,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.356242Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:8dd06b0ab24ae204f8e85e6b244e82b1d356d5bbd88bb7e09d0fe30d1fee8240","observation_id":"36c4d834-9e0a-4df7-abaf-300a928cdade","resolution":{"observed_at":"2026-08-08T00:12:41.234424Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.220761Z","title":"https://developer.arm.com/documentation/100095/0003/?lang=en","venue":null,"work_id":"27a0d13e-d94d-4ffd-8633-1525c1cba9ff","year":null},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":32,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.358883Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:3c4cb0f4141e311daf73a93c0b065be484b37561929921240549d7b01821c9d0","observation_id":"1ddcd4f8-295e-4fe1-952d-81397c25715a","resolution":{"observed_at":"2026-08-08T00:12:41.224402Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.209545Z","title":"https://www.intel.com/content/www/us/en/developer/articles/technical/ intel-sdm.html","venue":null,"work_id":"9fce81e3-ad57-4d3a-91a6-89f1f82a28f7","year":null},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":33,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.362437Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:55508fb948f2a43eb1f82619c071d142f812ff799c4213036abc2f615ed56445","observation_id":"e1636069-2ef5-4c64-b1ee-fa2d7de9affc","resolution":{"observed_at":"2026-08-08T00:12:41.213659Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"pages/1615476","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.683300Z","title":"https://riscv.atlassian.net/wiki/spaces/HOME/pages/16154769/RISC-V+ Technical+Specifications, 2024","venue":null,"work_id":"38768328-0116-4b83-8d76-a739fd6c35c8","year":2024},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":34,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.365966Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:b7edf4a6df8be6d146cab90772138edbf36b88bd719960c87a4d03dc465791bc","observation_id":"6a663881-3633-4ec7-81d2-6cccd587e48d","resolution":{"observed_at":"2026-08-08T00:12:40.690908Z","resolver_source":"raw_fallback","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.199657Z","title":"https://wiki.riscv.org/ display/HOME/Ratified+Extensions, 2024","venue":null,"work_id":"4aad88b8-761d-4c52-8eec-dbcabf583437","year":2024},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":35,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.369111Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:27cfa5cf705b5cfbf843642f5e09396f8ce17db9e7bfdbe6c23462b498d47df7","observation_id":"4155a68c-bbc0-4406-b54e-a4fb6ce98364","resolution":{"observed_at":"2026-08-08T00:12:41.203147Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.188354Z","title":"Torvalds and Linux Kernel Contributors","venue":null,"work_id":"fb9e6877-e81d-4ef9-8733-cb0065df917a","year":2024},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":36,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.372254Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:24571e1874b221d2a3c8cb309b2b24892dd31f41ef0c729926c3b3a7ac4f1c35","observation_id":"d9e9915b-640e-48b0-bf6d-004fc5f23ec9","resolution":{"observed_at":"2026-08-08T00:12:41.192683Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.178624Z","title":"Browne et al","venue":null,"work_id":"c28296ec-74b2-4e3d-ac81-1925b3342436","year":2000},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":37,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.375871Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:3ee0861a84bdcdd9baa61e534f34a57d3eb4ff1c081792c26d691104c887ea26","observation_id":"1aff4687-8b05-4d30-a238-f28977aac20f","resolution":{"observed_at":"2026-08-08T00:12:41.182322Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.170121Z","title":"Reinders.VTune Performance Analyzer Essentials","venue":null,"work_id":"9a622ad7-c0b8-4804-8ed1-febc45b65499","year":2005},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":38,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.378991Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:f0d126465b6cb0f20f9b683849753956114503ec4ed69cbd674286258215a5b2","observation_id":"b3795a6d-58c9-4d28-b5fb-7e4db3a42019","resolution":{"observed_at":"2026-08-08T00:12:41.173039Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.160293Z","title":"Tutorial: Linux kernel profiling with perf","venue":null,"work_id":"dd67be36-de1f-411e-b5d7-e12801632cda","year":2023},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":39,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.382119Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:41309e5d8af103ff7bd7b123c40d0a27523e546096c535989bea3fa508f3cc11","observation_id":"931f3633-d3e2-4884-b4a7-f0223037ecf8","resolution":{"observed_at":"2026-08-08T00:12:41.163715Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.149764Z","title":"uncore(5) — uncore performance coun- ters","venue":null,"work_id":"a166d269-f824-4266-a2ce-a193730ebcc0","year":2023},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":40,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.385348Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:cca6465caab2f6d625604b1031c0bb92512da2bd247662abdd298c5d27f7fb0c","observation_id":"ec7e2eaa-54a5-49f3-b039-7fd90e5aceed","resolution":{"observed_at":"2026-08-08T00:12:41.153583Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.140231Z","title":"NVIDIA Nsight Systems","venue":null,"work_id":"ec411b0d-930a-4c38-9b58-fb7213917229","year":2024},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":41,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.388559Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:13616a92623cda253f274ad778dc374c8efc1f366ccd646c84eece97e27ced98","observation_id":"2de4f49b-b48d-405b-bbb6-e732b5cef594","resolution":{"observed_at":"2026-08-08T00:12:41.143548Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2304.12072","last_updated":"2023-04-24T13:09:58Z","snapshot_observed_at":"2026-08-13T11:56:53.718716Z","submitted_at":"2023-04-24T13:09:58Z","title":"Exploration and Exploitation of Hidden PMU Events","version":1},"cited_work":{"arxiv_id":"2304.12072","doi":null,"metadata_source":"pith","pith_arxiv_id":"2304.12072","snapshot_observed_at":"2026-08-08T00:12:40.613439Z","title":"Exploration and Exploitation of Hidden PMU Events","venue":"cs.CR","work_id":"87d6481a-0184-408c-9e03-f301c8485d8c","year":2023},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":42,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.391673Z"},"links":{"cited_paper":"/paper/2304.12072","citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:14e790c5192b5bf467f7fafc54af9baf772a8b2f18f023537ca059c6c7782c91","observation_id":"ec126e2d-e7db-4c6d-82a2-34de91b002a9","resolution":{"observed_at":"2026-08-08T00:12:40.617303Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.130814Z","title":"Li et al","venue":null,"work_id":"185b190f-e5ad-4a1b-b010-f7b2c7de4448","year":2025},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":43,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.395691Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:6e7f63f34390e1f3f0084f9bae8bd8b492ef69504a9698e20a6ba352f0d81b4b","observation_id":"c9cf50f2-c626-4d1a-b7c7-bc69bf0d5dbf","resolution":{"observed_at":"2026-08-08T00:12:41.134181Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.121398Z","title":null,"venue":null,"work_id":"8dcb180a-438e-4a32-b56e-93c064770570","year":2003},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":44,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.399926Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:61abdaa4a732008ed8e38337900c30383a3034765989ada858264ea3cf143e28","observation_id":"1bed3894-eac5-4b98-832c-49cae1f1cd66","resolution":{"observed_at":"2026-08-08T00:12:41.124732Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.111127Z","title":"O’Callahan et al","venue":null,"work_id":"6b300208-680e-4aaf-9f3f-7ee88d014a92","year":2017},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":45,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.403446Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:f9d554313bf99841955ac3c5440a5b2515b374d65ce36c7489cb5b6157c0db51","observation_id":"45bb3e04-2b6d-4aa4-bec5-b2888db4326e","resolution":{"observed_at":"2026-08-08T00:12:41.114471Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.101316Z","title":"Bhatia et al","venue":null,"work_id":"09010c1b-bc52-4077-a2d2-9a965e608769","year":2008},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":46,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.406736Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:68e3a02ac958f4090ff71916988a1d03c893d63540a8188e51a6b985235c80b3","observation_id":"dd85a861-e43f-461c-9d7a-07b9bd2e6143","resolution":{"observed_at":"2026-08-08T00:12:41.104983Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.091342Z","title":null,"venue":null,"work_id":"e4a24413-d4aa-42e1-a7e7-fb52fa9291ef","year":2021},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":47,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.410755Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:71a5250b422b85981eab69da2682520dcfd1986132dc5e619b4238a72c7e8962","observation_id":"411c770a-c232-4301-9213-1fefba8cad44","resolution":{"observed_at":"2026-08-08T00:12:41.095104Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.082515Z","title":"Zhai et al","venue":null,"work_id":"55e619f7-15aa-4af3-b0b9-e93211ea27fa","year":2014},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":48,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.414213Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:7337e75e6eb5168ab8f75c7107f93d88b194e60b776457cf25fdd9704f21b51c","observation_id":"1cea3eae-4ffb-41e9-9c89-bdc5709a36b3","resolution":{"observed_at":"2026-08-08T00:12:41.085269Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.074043Z","title":"Dasari et al","venue":null,"work_id":"b47bedf1-b7ed-45d5-82eb-c7d1ba94bfce","year":2011},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":49,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.417619Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:25a8f6ec13b3a22438caccbacc639d19d5ff815e31293037abd918fdcfb0d7b4","observation_id":"3f2ebb43-a002-43f4-9980-a154c59b0087","resolution":{"observed_at":"2026-08-08T00:12:41.076826Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.064750Z","title":"D ´ıaz et al","venue":null,"work_id":"d78efa01-7e30-402b-a81d-9fade1a917c6","year":2018},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":50,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.420761Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:48b0bc3b893c7c6c3575343303c441300b1894dcacaaf2c02bd6c23a24c302d6","observation_id":"b40b7f6a-2d93-45d0-a42d-37690e6fd625","resolution":{"observed_at":"2026-08-08T00:12:41.068089Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.054122Z","title":"Program instrumentation options","venue":null,"work_id":"36dbe98e-7061-47a4-8454-3aacdf38ab08","year":2024},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":51,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.424250Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:5c14546e09bb6cd7cab7ee1fdf41bd3ba22a87bf6649b4f55faf2e02a68f4f03","observation_id":"37fd20cf-61ea-4643-9f69-4889185b3cca","resolution":{"observed_at":"2026-08-08T00:12:41.058189Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.044338Z","title":"Uprobe-tracer: Uprobe-based event tracing","venue":null,"work_id":"d1dbad9c-84c1-49dd-bde3-e63bee32d9b5","year":2024},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":52,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.427321Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:ef12a45aac48eda5469b687dacc006c8072de912c9d78c11c24d008f637ffb2a","observation_id":"3363e208-ec8c-430c-bfe7-974624256bf2","resolution":{"observed_at":"2026-08-08T00:12:41.047883Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.035065Z","title":"Uprobes in 3.5","venue":null,"work_id":"2e87a031-8e6d-4048-ba62-ff8dc22c5b63","year":2012},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":53,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.430840Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:65f6028e7917d1ace6b320ac35db57c579c7a02f23fa1bff83ac0602d43f4f62","observation_id":"c0e158ad-7575-47d0-888b-a81d4c6bea92","resolution":{"observed_at":"2026-08-08T00:12:41.038464Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.025355Z","title":"Fried et al","venue":null,"work_id":"99281937-8754-45f0-9128-813d7ca0ff1b","year":2020},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":54,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.434128Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:cc981436b05054011146ab5f023b67d4197265f43afb42be36e709d106031348","observation_id":"f4e03853-ed81-4d90-87fa-d8248208237d","resolution":{"observed_at":"2026-08-08T00:12:41.028832Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.015763Z","title":"Gifford et al","venue":null,"work_id":"0521fb95-fbff-47b1-8386-d018f6d9bec4","year":2021},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":55,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.437170Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:014fcf6f209e1a91a7a7ce5a6b8cb47ae056bf87840daddfb0c8c6427a02e7fc","observation_id":"014d51b0-b32b-4129-a868-7be20cc9f78d","resolution":{"observed_at":"2026-08-08T00:12:41.019135Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:41.005806Z","title":"Xu et al","venue":null,"work_id":"c0ae1505-ff74-41e2-86e4-c9880b749904","year":2018},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":56,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.440889Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:3c034edad82f1d225a072e76fbe449c4ea227bce1e5d39a5a13a7b13dcef0302","observation_id":"0b6eb8c0-144f-494e-8a80-3e868032af00","resolution":{"observed_at":"2026-08-08T00:12:41.009722Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.994641Z","title":"Nowotsch et al","venue":null,"work_id":"fe6bb929-858f-4820-a6eb-d79d6f720b89","year":2014},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":57,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.444080Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:b6015e0034ed316655b1dc04d9aba726b3c1b1443ca69eff9100b8d091fd507b","observation_id":"c7269de3-23b7-473e-849e-d2aaac010523","resolution":{"observed_at":"2026-08-08T00:12:40.998718Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.985003Z","title":"Cho et al","venue":null,"work_id":"bd7358b5-ea15-4f78-9ace-b18d084c60d3","year":2019},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":58,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.447074Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:431870c2eccb34cac941eb23d067d1a2964ba8322cb368b9ab42b0f92674d639","observation_id":"2870fc46-4d72-4168-9c32-233454d27638","resolution":{"observed_at":"2026-08-08T00:12:40.988198Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.976440Z","title":null,"venue":null,"work_id":"d1e7299e-78c3-4ddc-8575-be95c34df39e","year":2024},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":59,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.449800Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:c9efabd8de4a9479449ff99037d8dd696d121f3685f7ef186a3af4345a03aeae","observation_id":"a30233c4-762f-425d-8e9b-df4c38ee35e2","resolution":{"observed_at":"2026-08-08T00:12:40.979133Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.967351Z","title":"Intel Threat Detection Technology (Intel TDT)","venue":null,"work_id":"116b5dfb-273f-4746-9257-b68909a19f36","year":2024},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":60,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.452333Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:03e82645fb4604e9296dc46216817b6bf1d7e5f3285c00696aac94df03bb65a7","observation_id":"ed305bde-6091-41a4-ae46-4959838504d1","resolution":{"observed_at":"2026-08-08T00:12:40.970763Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.958236Z","title":"Saeed et al","venue":null,"work_id":"6ff84a77-3d31-4e76-a3e2-d67de0752688","year":2022},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":61,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.455124Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:9d1c862da40f58ad57f3292b043703bbe4985f90bd34451f330004dbd5580045","observation_id":"735f46da-e90a-4f15-95da-2c33a2f79c56","resolution":{"observed_at":"2026-08-08T00:12:40.961469Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.947857Z","title":"Cardona et al","venue":null,"work_id":"afa497c4-ddd7-49a7-9085-5c27997ef6bd","year":2019},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":62,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.457904Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:5449cd504283cc60648b6946f530650b25097c9a006d47b229ef874e5c1b6adb","observation_id":"5fceb338-ee29-43f7-9338-cee321b179c3","resolution":{"observed_at":"2026-08-08T00:12:40.952206Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.938688Z","title":"Wessman et al","venue":null,"work_id":"a4adf5c7-4145-436e-ba39-9324481eca13","year":2021},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":63,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.460416Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:8823c0b9e03c26371bfea5bc900f6af5fc9f2e82dd737c82b66799ae0a702326","observation_id":"9c8eba4d-240b-4ee3-a722-f8a98f30443f","resolution":{"observed_at":"2026-08-08T00:12:40.942050Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.929719Z","title":"de Lecea et al","venue":null,"work_id":"339666d4-d85f-4f5d-ad45-9dd6cdec9de9","year":2023},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":64,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.462998Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:120687edd523115034d5ff452bb2b1cda2063803db7c72954a211482e26e507d","observation_id":"e9225e93-03fe-414e-a70c-f44584f9abbf","resolution":{"observed_at":"2026-08-08T00:12:40.932862Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.920508Z","title":"Pujol et al","venue":null,"work_id":"bb9d9570-b479-4a50-a3c8-e334ddd85c59","year":2023},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":65,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.466056Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:d3bf76c4924ddbe415cf5db4fb1a4a6c57fec9a1d1d86f1ee97ee0291c661bc8","observation_id":"1360869a-9b73-43fd-a2c5-47fc5c2f1d70","resolution":{"observed_at":"2026-08-08T00:12:40.923725Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.910912Z","title":"Sullivan et al","venue":null,"work_id":"036e9cfa-8f92-4491-82df-384dfaeae3e0","year":2024},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":66,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.469066Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:9fb906e99839c8362553261e7b0d84b49d4dd9c7eae1e9bf6414dbfeedba38de","observation_id":"b9a065b5-61a8-491d-865e-c456a16851c8","resolution":{"observed_at":"2026-08-08T00:12:40.914336Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.901402Z","title":"Izhbirdeev et al","venue":null,"work_id":"fa88f401-5c13-4810-8d47-71837671a20e","year":2024},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":67,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.472099Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:c52ec9c098f2e85afdf19787439b98ebe5d430c8baf7cbff1483d74befa818d1","observation_id":"5dfa91d8-f385-4887-92ee-855f31400d01","resolution":{"observed_at":"2026-08-08T00:12:40.904773Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.890142Z","title":null,"venue":null,"work_id":"5a47fe48-d199-4c80-9d43-926b00e3a0a6","year":1991},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":68,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.475242Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:dbae1fd2cad606f263a291196a44a5834ab427354d2fd01ab373b815a48e8a3e","observation_id":"9e954637-7231-41d3-a8e3-379233521c10","resolution":{"observed_at":"2026-08-08T00:12:40.894482Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.879838Z","title":"Arm Architecture Reference Manual for A-profile architecture","venue":null,"work_id":"be73d6e3-d2d6-4c5a-8e10-669bbbe1eef0","year":2023},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":69,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.478532Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:4083b834c5517adf20190525d5137392d4cfac00c1c27744f87dad0c03a6bf5f","observation_id":"69e28c5a-f52a-4f53-a441-0a25f27cfb5e","resolution":{"observed_at":"2026-08-08T00:12:40.883191Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.870352Z","title":"https://developer.arm.com/Architectures/ System%20MMU%20Support","venue":null,"work_id":"52ec3a9f-cd9b-4a59-8375-472d7cc89899","year":null},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":70,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.481591Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:302b0f448520a87e060e69ebd0612b5099acb3cf5db000b3d1e0f98519629384","observation_id":"34a9f684-6d8d-4791-b7f5-ebb31a81d16d","resolution":{"observed_at":"2026-08-08T00:12:40.874245Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.861895Z","title":"https://wiki.riscv.org/display/HOME/ RISC-V+Technical+Specifications","venue":null,"work_id":"e4fc4098-2af9-4210-8c3d-2410a3594931","year":null},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":71,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.485521Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:5cd5ed41b60c7e65d671c39409edc7d211bf1927d501afea32345ca9f035b794","observation_id":"5fd4444a-0a82-4272-8271-c9d33f07130f","resolution":{"observed_at":"2026-08-08T00:12:40.864881Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.851779Z","title":"https://open-src-soc.org/2022-05/media/slides/ RISC-V-International-Day-2022-05-05-14h10-Perinne-Peresse.pdf","venue":null,"work_id":"fcb42b03-c466-47f6-8336-ea6ed5dec50f","year":2022},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":72,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.488680Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:27f64a3a31eab672314044db752d614f11f5b6fc47c5318b796bb7eb71e228eb","observation_id":"1523883b-c40b-4254-b70a-6261aa9676ec","resolution":{"observed_at":"2026-08-08T00:12:40.855197Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.841269Z","title":"Zaruba and L","venue":null,"work_id":"97f875e9-66d2-481b-90be-1c502b4dd69c","year":2019},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":73,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.491944Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:728c5b572a08ca6617518724166894b2407316202daef63ec24fbf72eff1f900","observation_id":"ea704fe2-d200-416a-b56c-13a0d8a5100c","resolution":{"observed_at":"2026-08-08T00:12:40.844982Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2009.05334","last_updated":"2021-11-11T14:42:36Z","snapshot_observed_at":"2026-08-13T06:02:11.821843Z","submitted_at":"2020-09-11T10:53:37Z","title":"An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication","version":2},"cited_work":{"arxiv_id":"2009.05334","doi":null,"metadata_source":"pith","pith_arxiv_id":"2009.05334","snapshot_observed_at":"2026-08-08T00:12:40.599983Z","title":"An Open-Source Platform for High-Performance Non-Coherent On-Chip Communication","venue":"cs.AR","work_id":"1170d5e8-fa1d-4e64-a7c5-673e5af5f411","year":2020},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":74,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.494971Z"},"links":{"cited_paper":"/paper/2009.05334","citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:3ef16cb8b3a558c420767e2304c1b0aac9aab93c5c0e495e434b5d537a16ccf5","observation_id":"399fbf71-70d4-494c-a7b5-53b6c6e7cb92","resolution":{"observed_at":"2026-08-08T00:12:40.603802Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.831141Z","title":"https://ibex-core","venue":null,"work_id":"e38c223a-250f-4658-a4ea-7fafe0fa6b59","year":null},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":75,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.498957Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:49bb4a12a773383548313076e30e9c7adf9b2d0efeb4ed1ecc7149fdb3a8d5be","observation_id":"d49bbe9c-20ba-4bf4-b0f9-95b5921f6ddc","resolution":{"observed_at":"2026-08-08T00:12:40.834921Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.821367Z","title":"Rossi et al","venue":null,"work_id":"9ecd465a-9371-4afa-adfc-a19f0fcc0c5a","year":2014},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":76,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.502257Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:5333b2ce553bd37346e15dfac1e32d116c5fb65ba5affe4de7ce193feee218f3","observation_id":"9c3d54f8-5aa5-4689-8445-30ceeb8e908d","resolution":{"observed_at":"2026-08-08T00:12:40.824820Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.810720Z","title":"PULP platform","venue":null,"work_id":"14eeaecc-2d47-48e2-8de2-5ae0907e9050","year":2014},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":77,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.505611Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:abd6cf0d72638bff5aae9e02041409763ba9647620229b060027df71869d3a8b","observation_id":"f4c6cfab-f5ef-4d09-a1b8-05df1bd35bf2","resolution":{"observed_at":"2026-08-08T00:12:40.814345Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.799958Z","title":"Valente et al","venue":null,"work_id":"259e07b1-4945-42dd-8ff8-df6feafadd82","year":2023},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":78,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.508824Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:20f974406100777882e02a33cefd4f4dfeafea253972965e9e9269d4fb379a3a","observation_id":"4c5b70cd-6f6a-45bb-9b8b-660d9d10bf24","resolution":{"observed_at":"2026-08-08T00:12:40.803465Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.789649Z","title":"Valente et al","venue":null,"work_id":"41f0b733-8983-4b90-b88e-a3949a429043","year":2024},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":79,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.512041Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:2c74cd9676852c41e940d5fd179f934b066c6f1a7bd26183f40bc561007a28b3","observation_id":"82e958d6-aeb1-46b2-97b7-f3e63b622c6c","resolution":{"observed_at":"2026-08-08T00:12:40.793109Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.778802Z","title":"Sinigaglia et al","venue":null,"work_id":"45ab9a7a-e23d-47db-abe3-8c91a0cfb813","year":2026},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":80,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.515177Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:03eb72f19ebe803b3f55bff89244840d6cbe96497dd546ca05d7bdc5454d93b5","observation_id":"c20023eb-6bc4-4abc-bbd2-e9010b04636f","resolution":{"observed_at":"2026-08-08T00:12:40.782580Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.768237Z","title":"https://www","venue":null,"work_id":"4b5b3c76-7fa5-4c72-89c2-1d51c253761c","year":null},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":81,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.518919Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:b37e1e6f280b12e2be77cbcc9e0ebb9f1d0e35b386c8f7fbc5bddd84b4556bdb","observation_id":"5ab3ff6d-f76e-4271-a61a-6fbeda33648b","resolution":{"observed_at":"2026-08-08T00:12:40.772234Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2407.19895","last_updated":"2024-08-12T07:47:28Z","snapshot_observed_at":"2026-08-12T23:12:58.370078Z","submitted_at":"2024-07-29T11:17:26Z","title":"Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor","version":2},"cited_work":{"arxiv_id":"2407.19895","doi":null,"metadata_source":"pith","pith_arxiv_id":"2407.19895","snapshot_observed_at":"2026-08-08T00:12:40.585489Z","title":"Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor","venue":"eess.SY","work_id":"3b1a9332-1d8b-426f-9ba9-76a617e2a866","year":2024},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":82,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.522310Z"},"links":{"cited_paper":"/paper/2407.19895","citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:0529b4639652a74d42e020c135139832855cf499d0057de870c88fe38cc91b60","observation_id":"d92610c0-99db-4376-aa8a-2b40b08572b4","resolution":{"observed_at":"2026-08-08T00:12:40.589804Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.758659Z","title":"AXI LLC: A Parameterizable AXI4- Compliant Last-Level Cache","venue":null,"work_id":"0ac9d201-5de9-4116-991d-e43bf8f8138a","year":null},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":83,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.525874Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:9d7bd807c76266d4ee60217d26afd320b773075576249438f71d8f0277146f04","observation_id":"c3d6c090-c399-4d03-b8e0-4a9d9d965cb8","resolution":{"observed_at":"2026-08-08T00:12:40.761741Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.743075Z","title":"Newsome et al.RISC-V Debug Specification, Document Version 1.0- STABLE","venue":null,"work_id":"1b9ecab9-1fd9-444b-9e9a-ffdc76eda9b6","year":2019},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":84,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.532179Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:9999491f2378fb56884321fa040eb4e33df418e1fed0e3cbafab0b46a214a7b1","observation_id":"54d66f07-ab8b-4c07-a855-cd4f2b870254","resolution":{"observed_at":"2026-08-08T00:12:40.746192Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.734006Z","title":"Yun et al","venue":null,"work_id":"3a9d0c3a-e584-490c-8f5b-2719b3ff3694","year":2014},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":85,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.535374Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:e86073adc2215b00420592c9df242a0f9e3d34c65ed2ffbd8b2b69958bd0a2bd","observation_id":"318465dd-afbe-4c38-9680-d67cab78ebd7","resolution":{"observed_at":"2026-08-08T00:12:40.737303Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.722659Z","title":null,"venue":null,"work_id":"906eb699-3a63-4e11-abdb-a5033968de23","year":2009},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":86,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.538429Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:7845ed3e9ab02c7c42daf936d67aa9983dcf5e7fc057005ab36088534df2bcb4","observation_id":"571a95d9-8aa4-4c2c-b740-00b786bc1766","resolution":{"observed_at":"2026-08-08T00:12:40.726847Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.712740Z","title":null,"venue":null,"work_id":"0884751f-ddd1-4ab2-bd4d-686870d61b1e","year":2026},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":87,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.541392Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:f6929b0a660706aa0e4e727e20550cd33f41c8c4505926170abe20aa2d50e45a","observation_id":"43e3d8e4-543e-46aa-b359-63f067c1f620","resolution":{"observed_at":"2026-08-08T00:12:40.716043Z","resolver_source":"raw_fallback","status":"unresolved"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.5281/zenodo.21543106","metadata_source":"doi_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.571743Z","title":null,"venue":null,"work_id":"d8e6f65e-2383-4757-b3b0-b3271e477289","year":2026},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":88,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.544529Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:99af1a61540dc4b2d563c36aec4d7ba514e9606c746e1a84d40b1cb6069f5095","observation_id":"85b29270-1f24-4d0a-9fba-d467f6dc03fd","resolution":{"observed_at":"2026-08-08T00:12:40.575851Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-13T06:32:02.005865+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-08T00:12:40.528972Z","title":null,"venue":null,"work_id":null,"year":2026},"citing_paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","version":1},"reference_index":2025,"source":"pdf_text","source_observed_at":"2026-08-08T00:12:40.528972Z"},"links":{"citing_paper":"/paper/2608.04247"},"observation_digest":"sha256:3d5ccd3c86595f2a91e01b66ab7fb5a982e6f234e8162cfb0503237a3135628d","observation_id":"75ebf2ff-52fa-4cf1-8dd8-c6f04df7c89c","resolution":{"observed_at":"2026-08-08T00:12:40.528972Z","resolver_source":null,"status":"parse_uncertain"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}}],"paper":{"arxiv_id":"2608.04247","last_updated":"2026-08-04T21:57:50Z","latest_version":1,"primary_category":"cs.AR","snapshot_observed_at":"2026-08-08T23:11:19.109720Z","submitted_at":"2026-08-04T21:57:50Z","title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs"},"reference_resolution":{"displayed":89,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":1,"unresolved":16,"verified_exact":6,"verified_fuzzy":66},"total_outbound_references":89},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-13T06:32:02.005865+00:00","source":"crossref"},{"observed_at":"2026-08-13T06:31:53.387327+00:00","source":"retraction_watch"}],"thesis":"As of 13 August 2026, this Paper Citation Record lists 89 of 89 outbound references and 0 inbound Pith citation observations for arXiv:2608.04247."}