{"as_of":"2026-08-17T19:06:00Z","caps":{"database_statements":6,"inbound":100,"outbound":100},"context_digest":"sha256:16484813e8ec55e2cb59d77d6aeec0cf1a246847b902a19d5bfdfa156513e958","coverage":[{"denominator":20,"lane":"reference_resolution","note":"Typed states for the displayed outbound observations.","records_observed":20,"source":"paper_references, paper_reference_links","source_observed_at":"2026-08-16T00:08:22.586199Z","state":"measured"},{"denominator":20,"lane":"standing_notices","note":"One-hop event checks from named stored sources.","records_observed":20,"source":"scholarly_work_events, retraction_status_cache","source_observed_at":"2026-08-17T06:30:58.91139+00:00","state":"measured"},{"denominator":0,"lane":"inbound_itemization","note":"Pith citing papers itemized under the disclosed page cap.","records_observed":0,"source":"paper_references, paper_reference_links","source_observed_at":null,"state":"measured"},{"denominator":1,"lane":"external_citation_measurements","note":"A source-named dated measurement, never combined with another source.","records_observed":0,"source":"cited_works","source_observed_at":null,"state":"measured"}],"external_citation_measurements":[],"inbound":[],"links":{"evidence":"/evidence","html":"/paper/2608.12635/citation-record","integrity":"/paper/2608.12635/integrity","json":"/paper/2608.12635/citation-record.json","paper":"/paper/2608.12635"},"outbound":[{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-16T00:08:23.571294Z","title":"MetRex: A benchmark for Verilog code metric reasoning using LLMs","venue":null,"work_id":"f755aade-ad50-4a99-b0b1-a395c5714aad","year":null},"citing_paper":{"arxiv_id":"2608.12635","last_updated":"2026-08-12T22:50:11Z","snapshot_observed_at":"2026-08-16T23:10:44.570633Z","submitted_at":"2026-08-12T22:50:11Z","title":"GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing","version":1},"reference_index":1,"source":"pdf_text","source_observed_at":"2026-08-16T00:08:22.444372Z"},"links":{"citing_paper":"/paper/2608.12635"},"observation_digest":"sha256:e58033d9394fb4d3d1fd63189bde96ac5bdacba1eb5cecfc14488f3750726355","observation_id":"4c591e76-4e3b-42ea-9a5c-6b4357891d6e","resolution":{"observed_at":"2026-08-16T00:08:23.577879Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2503.21971","last_updated":"2025-06-10T22:20:25Z","snapshot_observed_at":"2026-08-16T21:52:22.951203Z","submitted_at":"2025-03-27T20:35:09Z","title":"RocketPPA: Code-Level Power, Performance, and Area Prediction via LLM and Mixture of Experts","version":3},"cited_work":{"arxiv_id":"2503.21971","doi":null,"metadata_source":"pith","pith_arxiv_id":"2503.21971","snapshot_observed_at":"2026-08-16T00:08:23.472863Z","title":"RocketPPA: Code-Level Power, Performance, and Area Prediction via LLM and Mixture of Experts","venue":"cs.LG","work_id":"a7c21f14-7054-4e9d-872b-cc009651c36b","year":2025},"citing_paper":{"arxiv_id":"2608.12635","last_updated":"2026-08-12T22:50:11Z","snapshot_observed_at":"2026-08-16T23:10:44.570633Z","submitted_at":"2026-08-12T22:50:11Z","title":"GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing","version":1},"reference_index":2,"source":"pdf_text","source_observed_at":"2026-08-16T00:08:22.450844Z"},"links":{"cited_paper":"/paper/2503.21971","citing_paper":"/paper/2608.12635"},"observation_digest":"sha256:3f349aed5b01804bf268363a2f3b93d4698fb9b68d5a9c87f80ebebc9677bb96","observation_id":"22600bf7-6555-4768-90fb-db5928366b7a","resolution":{"observed_at":"2026-08-16T00:08:23.479135Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2507.06376","last_updated":"2025-07-08T20:27:08Z","snapshot_observed_at":"2026-08-15T18:49:06.761878Z","submitted_at":"2025-07-08T20:27:08Z","title":"SLDB: An End-To-End Heterogeneous System-on-Chip Benchmark Suite for LLM-Aided Design","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2507.06376","snapshot_observed_at":"2026-08-16T00:08:22.457101Z","title":null,"venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2608.12635","last_updated":"2026-08-12T22:50:11Z","snapshot_observed_at":"2026-08-16T23:10:44.570633Z","submitted_at":"2026-08-12T22:50:11Z","title":"GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing","version":1},"reference_index":3,"source":"pdf_text","source_observed_at":"2026-08-16T00:08:22.457101Z"},"links":{"cited_paper":"/paper/2507.06376","citing_paper":"/paper/2608.12635"},"observation_digest":"sha256:d65e5831caa17ce0e5997e4cc92818704e7b1b0afac104dd452840955fdce285","observation_id":"80b4e30c-51b9-4f17-b638-86e6dbe8c6e2","resolution":{"observed_at":"2026-08-16T00:08:22.457101Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-16T00:08:22.463791Z","title":"DeMillo, Richard J","venue":null,"work_id":null,"year":1978},"citing_paper":{"arxiv_id":"2608.12635","last_updated":"2026-08-12T22:50:11Z","snapshot_observed_at":"2026-08-16T23:10:44.570633Z","submitted_at":"2026-08-12T22:50:11Z","title":"GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing","version":1},"reference_index":4,"source":"pdf_text","source_observed_at":"2026-08-16T00:08:22.463791Z"},"links":{"citing_paper":"/paper/2608.12635"},"observation_digest":"sha256:ebdf1ec68473ebbbee73cfa621789cb696e6d7a0bab5b7ebfef58150c1a749ed","observation_id":"bba2b2cc-8c27-449c-aa98-86346565dee3","resolution":{"observed_at":"2026-08-16T00:08:22.463791Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":"10.1155/2015/256474","metadata_source":"doi_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-16T00:08:22.644749Z","title":"Functional testbench qualification by mutation analysis.VLSI Design, 2015:256474, 2015","venue":null,"work_id":"c9270ebf-5004-4d8e-bb05-17f13f79771b","year":2015},"citing_paper":{"arxiv_id":"2608.12635","last_updated":"2026-08-12T22:50:11Z","snapshot_observed_at":"2026-08-16T23:10:44.570633Z","submitted_at":"2026-08-12T22:50:11Z","title":"GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing","version":1},"reference_index":5,"source":"pdf_text","source_observed_at":"2026-08-16T00:08:22.470788Z"},"links":{"citing_paper":"/paper/2608.12635"},"observation_digest":"sha256:335d0d0fea9d2c80dce650e3646cc54185230d201a3efa3fbca632a6d329b5aa","observation_id":"ae0646cd-4d84-447c-b5a9-b427ea37d066","resolution":{"observed_at":"2026-08-16T00:08:22.655912Z","resolver_source":"doi","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":"2601.07593","doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-16T00:08:23.289294Z","title":"GRPO with state mutations: Improving LLM-based hardware test plan generation.arXiv preprint arXiv:2601.07593, 2026","venue":null,"work_id":"bb11691f-49c8-4ac2-8a28-43d1a8b6111e","year":2026},"citing_paper":{"arxiv_id":"2608.12635","last_updated":"2026-08-12T22:50:11Z","snapshot_observed_at":"2026-08-16T23:10:44.570633Z","submitted_at":"2026-08-12T22:50:11Z","title":"GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing","version":1},"reference_index":6,"source":"pdf_text","source_observed_at":"2026-08-16T00:08:22.476727Z"},"links":{"citing_paper":"/paper/2608.12635"},"observation_digest":"sha256:f7af60268393896f7f7a4b06ab7b18dc5d6a42524fca9630ebeafa96c65da39f","observation_id":"e0bd818b-5f3b-41e5-aa56-6eb3503253d2","resolution":{"observed_at":"2026-08-16T00:08:23.329250Z","resolver_source":"raw_fallback","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2309.07544","last_updated":"2023-12-10T00:23:04Z","snapshot_observed_at":"2026-08-16T19:10:26.934221Z","submitted_at":"2023-09-14T09:15:34Z","title":"VerilogEval: Evaluating Large Language Models for Verilog Code Generation","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2309.07544","snapshot_observed_at":"2026-08-16T00:08:22.482762Z","title":"VerilogEval: Evaluating large language models for Verilog code generation","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2608.12635","last_updated":"2026-08-12T22:50:11Z","snapshot_observed_at":"2026-08-16T23:10:44.570633Z","submitted_at":"2026-08-12T22:50:11Z","title":"GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing","version":1},"reference_index":7,"source":"pdf_text","source_observed_at":"2026-08-16T00:08:22.482762Z"},"links":{"cited_paper":"/paper/2309.07544","citing_paper":"/paper/2608.12635"},"observation_digest":"sha256:1fd244785e5edb1146939105821e020d18a08591d70aef41417ef7c8650f8a06","observation_id":"9ff95317-56f7-4491-8380-fbc94ddc4c68","resolution":{"observed_at":"2026-08-16T00:08:22.482762Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2503.15112","last_updated":"2025-03-19T11:12:53Z","snapshot_observed_at":"2026-08-16T19:14:53.392272Z","submitted_at":"2025-03-19T11:12:53Z","title":"OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2503.15112","snapshot_observed_at":"2026-08-16T00:08:22.489390Z","title":"OpenLLM-RTL: Open dataset and benchmark for LLM-aided design RTL generation.arXiv preprint arXiv:2503.15112, 2025","venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2608.12635","last_updated":"2026-08-12T22:50:11Z","snapshot_observed_at":"2026-08-16T23:10:44.570633Z","submitted_at":"2026-08-12T22:50:11Z","title":"GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing","version":1},"reference_index":8,"source":"pdf_text","source_observed_at":"2026-08-16T00:08:22.489390Z"},"links":{"cited_paper":"/paper/2503.15112","citing_paper":"/paper/2608.12635"},"observation_digest":"sha256:7cc80584b72e83b6ad41c0cb7c7d0bce6822e8472aa457d30318cb9e2d46948a","observation_id":"ddbc3ea5-1f4d-4be8-bff1-0d8271cd981d","resolution":{"observed_at":"2026-08-16T00:08:22.489390Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2308.05345","last_updated":"2023-11-11T07:53:10Z","snapshot_observed_at":"2026-08-16T15:09:29.057310Z","submitted_at":"2023-08-10T05:24:41Z","title":"RTLLM: An Open-Source Benchmark for Design RTL Generation with Large Language Model","version":3},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2308.05345","snapshot_observed_at":"2026-08-16T00:08:22.494120Z","title":"RTLLM: An open-source benchmark for design RTL generation with large language model","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2608.12635","last_updated":"2026-08-12T22:50:11Z","snapshot_observed_at":"2026-08-16T23:10:44.570633Z","submitted_at":"2026-08-12T22:50:11Z","title":"GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing","version":1},"reference_index":9,"source":"pdf_text","source_observed_at":"2026-08-16T00:08:22.494120Z"},"links":{"cited_paper":"/paper/2308.05345","citing_paper":"/paper/2608.12635"},"observation_digest":"sha256:ec418906ac6b2775918e87c8ebd0093f7da2c3d787915be793e1065dacc52e5c","observation_id":"1106c16c-9584-4fcf-abbe-4ceb298612f5","resolution":{"observed_at":"2026-08-16T00:08:22.494120Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2506.14074","last_updated":"2025-06-17T00:11:13Z","snapshot_observed_at":"2026-08-16T21:51:53.107849Z","submitted_at":"2025-06-17T00:11:13Z","title":"Comprehensive Verilog Design Problems: A Next-Generation Benchmark Dataset for Evaluating Large Language Models and Agents on RTL Design and Verification","version":1},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2506.14074","snapshot_observed_at":"2026-08-16T00:08:22.502422Z","title":null,"venue":null,"work_id":null,"year":2025},"citing_paper":{"arxiv_id":"2608.12635","last_updated":"2026-08-12T22:50:11Z","snapshot_observed_at":"2026-08-16T23:10:44.570633Z","submitted_at":"2026-08-12T22:50:11Z","title":"GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing","version":1},"reference_index":10,"source":"pdf_text","source_observed_at":"2026-08-16T00:08:22.502422Z"},"links":{"cited_paper":"/paper/2506.14074","citing_paper":"/paper/2608.12635"},"observation_digest":"sha256:2c805396db9acf465f182b0b8aae8821f6f35f9d245bae8587d21865e6d9adbd","observation_id":"c31426c2-2a29-4db9-a2d4-bdfdb26e00af","resolution":{"observed_at":"2026-08-16T00:08:22.502422Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2408.11053","last_updated":"2025-02-03T19:29:27Z","snapshot_observed_at":"2026-08-16T21:53:20.535426Z","submitted_at":"2024-08-20T17:58:56Z","title":"Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2408.11053","snapshot_observed_at":"2026-08-16T00:08:22.507720Z","title":"Revisiting VerilogEval: A year of improvements in large-language models for hardware code generation.arXiv preprint arXiv:2408.11053, 2024","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2608.12635","last_updated":"2026-08-12T22:50:11Z","snapshot_observed_at":"2026-08-16T23:10:44.570633Z","submitted_at":"2026-08-12T22:50:11Z","title":"GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing","version":1},"reference_index":11,"source":"pdf_text","source_observed_at":"2026-08-16T00:08:22.507720Z"},"links":{"cited_paper":"/paper/2408.11053","citing_paper":"/paper/2608.12635"},"observation_digest":"sha256:74260269a4c4199ca55a59b97a6f916dbad4a672c8e74af9aaacfc6a222f9197","observation_id":"2e96c36b-5071-44cc-8e34-8cbde36808e1","resolution":{"observed_at":"2026-08-16T00:08:22.507720Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2508.06047","last_updated":"2025-08-08T06:12:00Z","snapshot_observed_at":"2026-08-15T03:24:11.179213Z","submitted_at":"2025-08-08T06:12:00Z","title":"ArchXBench: A Complex Digital Systems Benchmark Suite for LLM Driven RTL Synthesis","version":1},"cited_work":{"arxiv_id":"2508.06047","doi":null,"metadata_source":"pith","pith_arxiv_id":"2508.06047","snapshot_observed_at":"2026-08-16T00:08:23.073189Z","title":"ArchXBench: A Complex Digital Systems Benchmark Suite for LLM Driven RTL Synthesis","venue":"cs.AR","work_id":"1fa208b4-ead0-4f67-b9fa-4c93fd06a9a6","year":2025},"citing_paper":{"arxiv_id":"2608.12635","last_updated":"2026-08-12T22:50:11Z","snapshot_observed_at":"2026-08-16T23:10:44.570633Z","submitted_at":"2026-08-12T22:50:11Z","title":"GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing","version":1},"reference_index":12,"source":"pdf_text","source_observed_at":"2026-08-16T00:08:22.514289Z"},"links":{"cited_paper":"/paper/2508.06047","citing_paper":"/paper/2608.12635"},"observation_digest":"sha256:c0ef8e369961ee0df64eaceba2273acdbabf146fb2f912359c095fd3fd2804ee","observation_id":"390f99aa-4f65-4756-80d4-8f32c4e23f32","resolution":{"observed_at":"2026-08-16T00:08:23.092167Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2407.03891","last_updated":"2024-08-20T09:19:07Z","snapshot_observed_at":"2026-08-16T21:53:21.571955Z","submitted_at":"2024-07-04T12:33:56Z","title":"AutoBench: Automatic Testbench Generation and Evaluation Using LLMs for HDL Design","version":2},"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":"2407.03891","snapshot_observed_at":"2026-08-16T00:08:22.522912Z","title":"AutoBench: Automatic testbench generation and evaluation using LLMs for HDL design.arXiv preprint arXiv:2407.03891, 2024","venue":null,"work_id":null,"year":2024},"citing_paper":{"arxiv_id":"2608.12635","last_updated":"2026-08-12T22:50:11Z","snapshot_observed_at":"2026-08-16T23:10:44.570633Z","submitted_at":"2026-08-12T22:50:11Z","title":"GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing","version":1},"reference_index":13,"source":"pdf_text","source_observed_at":"2026-08-16T00:08:22.522912Z"},"links":{"cited_paper":"/paper/2407.03891","citing_paper":"/paper/2608.12635"},"observation_digest":"sha256:e04acee88ed9593c54db3f89ee34002eccbc4fb6674f4b160cfab221bc9658b2","observation_id":"16ac31ef-06f5-4209-bc0a-1eedab0aef26","resolution":{"observed_at":"2026-08-16T00:08:22.522912Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":{"arxiv_id":"2506.07945","last_updated":"2025-07-15T16:24:28Z","snapshot_observed_at":"2026-08-16T16:46:16.968583Z","submitted_at":"2025-06-09T17:10:47Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","version":2},"cited_work":{"arxiv_id":"2506.07945","doi":null,"metadata_source":"pith","pith_arxiv_id":"2506.07945","snapshot_observed_at":"2026-08-16T00:08:22.994743Z","title":"ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols","venue":"cs.AR","work_id":"7ed56d30-b3ee-4868-a431-2bb081d69783","year":2025},"citing_paper":{"arxiv_id":"2608.12635","last_updated":"2026-08-12T22:50:11Z","snapshot_observed_at":"2026-08-16T23:10:44.570633Z","submitted_at":"2026-08-12T22:50:11Z","title":"GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing","version":1},"reference_index":14,"source":"pdf_text","source_observed_at":"2026-08-16T00:08:22.536820Z"},"links":{"cited_paper":"/paper/2506.07945","citing_paper":"/paper/2608.12635"},"observation_digest":"sha256:85edd536509e81041a3fb39adb82efa5fee7acebc5448b45b595bd483099d0dc","observation_id":"13e3f751-e869-402a-a270-69465a40347c","resolution":{"observed_at":"2026-08-16T00:08:23.025089Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2607.13079","last_updated":"2026-07-20T02:21:21Z","snapshot_observed_at":"2026-08-15T12:46:11.757537Z","submitted_at":"2026-07-12T23:38:38Z","title":"ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation","version":2},"cited_work":{"arxiv_id":"2607.13079","doi":null,"metadata_source":"pith","pith_arxiv_id":"2607.13079","snapshot_observed_at":"2026-08-16T00:08:22.952031Z","title":"ChipVerilog: A Large-Scale OpenCores-Derived Benchmark for LLM-Based Verilog RTL Generation","venue":"cs.AR","work_id":"f14b4645-4742-4f67-b306-94d3362bfe21","year":2026},"citing_paper":{"arxiv_id":"2608.12635","last_updated":"2026-08-12T22:50:11Z","snapshot_observed_at":"2026-08-16T23:10:44.570633Z","submitted_at":"2026-08-12T22:50:11Z","title":"GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing","version":1},"reference_index":15,"source":"pdf_text","source_observed_at":"2026-08-16T00:08:22.544765Z"},"links":{"cited_paper":"/paper/2607.13079","citing_paper":"/paper/2608.12635"},"observation_digest":"sha256:09107229349f141a4055683c8e805b9ceed94f6ad2565b353c7231a199f31fc5","observation_id":"de2f58a2-155f-410f-b59b-259f33e8ebb2","resolution":{"observed_at":"2026-08-16T00:08:22.959005Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2606.08976","last_updated":"2026-06-08T03:21:33Z","snapshot_observed_at":"2026-08-13T04:48:37.554753Z","submitted_at":"2026-06-08T03:21:33Z","title":"RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models","version":1},"cited_work":{"arxiv_id":"2606.08976","doi":null,"metadata_source":"pith","pith_arxiv_id":"2606.08976","snapshot_observed_at":"2026-08-16T00:08:22.899051Z","title":"RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models","venue":"cs.AI","work_id":"5861bd23-c288-4fa2-be12-6db156f95d09","year":2026},"citing_paper":{"arxiv_id":"2608.12635","last_updated":"2026-08-12T22:50:11Z","snapshot_observed_at":"2026-08-16T23:10:44.570633Z","submitted_at":"2026-08-12T22:50:11Z","title":"GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing","version":1},"reference_index":16,"source":"pdf_text","source_observed_at":"2026-08-16T00:08:22.550834Z"},"links":{"cited_paper":"/paper/2606.08976","citing_paper":"/paper/2608.12635"},"observation_digest":"sha256:dcb629866f995ba29bc65c6ea6df79def7525f05df650d4da80dfaf2b982d473","observation_id":"2d8cc2c7-136f-473c-9ba7-77dc1e58211e","resolution":{"observed_at":"2026-08-16T00:08:22.909224Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":{"arxiv_id":"2605.15537","last_updated":"2026-05-15T02:17:46Z","snapshot_observed_at":"2026-08-15T17:04:05.201143Z","submitted_at":"2026-05-15T02:17:46Z","title":"RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision","version":1},"cited_work":{"arxiv_id":"2605.15537","doi":null,"metadata_source":"pith","pith_arxiv_id":"2605.15537","snapshot_observed_at":"2026-08-16T00:08:22.842928Z","title":"RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision","venue":"cs.AI","work_id":"e9105d97-79b1-4f4c-88dd-1a614cef970f","year":2026},"citing_paper":{"arxiv_id":"2608.12635","last_updated":"2026-08-12T22:50:11Z","snapshot_observed_at":"2026-08-16T23:10:44.570633Z","submitted_at":"2026-08-12T22:50:11Z","title":"GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing","version":1},"reference_index":17,"source":"pdf_text","source_observed_at":"2026-08-16T00:08:22.557841Z"},"links":{"cited_paper":"/paper/2605.15537","citing_paper":"/paper/2608.12635"},"observation_digest":"sha256:8876005424ff2d74dbaf5d4c3eca562d074b6392a79653c7eb7aa0677f014a45","observation_id":"5a7307a0-b131-4a80-987d-61484c45086b","resolution":{"observed_at":"2026-08-16T00:08:22.851315Z","resolver_source":"local_arxiv","status":"verified_exact"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-16T00:08:22.568906Z","title":"Mantra: Mutation testing of hardware design code based on real bugs","venue":null,"work_id":null,"year":2023},"citing_paper":{"arxiv_id":"2608.12635","last_updated":"2026-08-12T22:50:11Z","snapshot_observed_at":"2026-08-16T23:10:44.570633Z","submitted_at":"2026-08-12T22:50:11Z","title":"GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing","version":1},"reference_index":18,"source":"pdf_text","source_observed_at":"2026-08-16T00:08:22.568906Z"},"links":{"citing_paper":"/paper/2608.12635"},"observation_digest":"sha256:f4d0c98ea82b10d5d49e92738a72e96f9e282785bc6f70679fd8ac6215be0177","observation_id":"18c02be8-bd27-4b15-be65-ee9703af04e5","resolution":{"observed_at":"2026-08-16T00:08:22.568906Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":"raw_reference","pith_arxiv_id":null,"snapshot_observed_at":"2026-08-16T00:08:23.493066Z","title":"Introduction to Mutation Coverage with Yosys (MCY)","venue":null,"work_id":"88d7b20f-424c-4bff-8899-46c575cc6b65","year":2021},"citing_paper":{"arxiv_id":"2608.12635","last_updated":"2026-08-12T22:50:11Z","snapshot_observed_at":"2026-08-16T23:10:44.570633Z","submitted_at":"2026-08-12T22:50:11Z","title":"GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing","version":1},"reference_index":19,"source":"pdf_text","source_observed_at":"2026-08-16T00:08:22.580017Z"},"links":{"citing_paper":"/paper/2608.12635"},"observation_digest":"sha256:3a70f280ea490469c7f463cc21e06a1aa498fa9fd692b08676f312db40e0889c","observation_id":"8237c536-c7bd-45c9-b4ac-95a94b56a1fe","resolution":{"observed_at":"2026-08-16T00:08:23.522081Z","resolver_source":"raw_fallback","status":"verified_fuzzy"},"standing_notice":{"events":[],"observation":"No event found in the named queried sources as of 2026-08-17T06:30:58.91139+00:00.","reason":null,"source_receipts":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"state":"measured"}},{"citation":{"cited_paper":null,"cited_work":{"arxiv_id":null,"doi":null,"metadata_source":null,"pith_arxiv_id":null,"snapshot_observed_at":"2026-08-16T00:08:22.586199Z","title":"ChipBench: A next-step benchmark for evaluating LLM performance in AI-aided chip design.arXiv preprint arXiv:2601.21448, 2026","venue":null,"work_id":null,"year":2026},"citing_paper":{"arxiv_id":"2608.12635","last_updated":"2026-08-12T22:50:11Z","snapshot_observed_at":"2026-08-16T23:10:44.570633Z","submitted_at":"2026-08-12T22:50:11Z","title":"GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing","version":1},"reference_index":20,"source":"pdf_text","source_observed_at":"2026-08-16T00:08:22.586199Z"},"links":{"citing_paper":"/paper/2608.12635"},"observation_digest":"sha256:839ad21ae90460098ecbbbee0ca801b96fdf8a2e8c3f249c801231b743c1be6c","observation_id":"a928f4af-56c1-46f8-b1d1-d6a1cf2aac05","resolution":{"observed_at":"2026-08-16T00:08:22.586199Z","resolver_source":null,"status":"unresolved"},"standing_notice":{"events":[],"reason":"canonical_work_link_unavailable","source_receipts":[],"state":"unavailable"}}],"paper":{"arxiv_id":"2608.12635","last_updated":"2026-08-12T22:50:11Z","latest_version":1,"primary_category":"cs.AR","snapshot_observed_at":"2026-08-16T23:10:44.570633Z","submitted_at":"2026-08-12T22:50:11Z","title":"GateTruth: Auditing the Rigor of RTL Design Benchmarks via Mutation Testing"},"reference_resolution":{"displayed":20,"state_counts":{"malformed_identifier":0,"metadata_mismatch":0,"parse_uncertain":0,"unresolved":10,"verified_exact":8,"verified_fuzzy":2},"total_outbound_references":20},"refusal":"A citation records a reference. It does not transfer a finding from one paper to another.","schema":"pith.paper-citation-record.v1","standing_sources":[{"observed_at":"2026-08-17T06:30:58.91139+00:00","source":"crossref"},{"observed_at":"2026-08-17T06:30:54.323127+00:00","source":"retraction_watch"}],"thesis":"As of 17 August 2026, this Paper Citation Record lists 20 of 20 outbound references and 0 inbound Pith citation observations for arXiv:2608.12635."}