{"record_type":"pith_number_record","schema_url":"https://pith.science/schemas/pith-number/v1.json","pith_number":"pith:2024:BFKXBXHATLW7RT4NJGEVWMVABK","short_pith_number":"pith:BFKXBXHA","schema_version":"1.0","canonical_sha256":"095570dce09aedf8cf8d49895b32a00a896c7399d3248131a4898c9ebeabb674","source":{"kind":"arxiv","id":"2407.19895","version":2},"attestation_state":"computed","paper":{"title":"Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor","license":"http://arxiv.org/licenses/nonexclusive-distrib/1.0/","headline":"","cross_cats":["cs.SY"],"primary_cat":"eess.SY","authors_text":"Abdul Basit Sajjad, Davide Rossi, Enrico Zelioli, Gianmarco Ottavi, Luca Benini, Luca Valente, Massimiliano Giacometti, Nils Wistoff, Riccardo Tedeschi","submitted_at":"2024-07-29T11:17:26Z","abstract_excerpt":"Symmetric Multi-Processing (SMP) based on cache coherency is crucial for high-end embedded systems like automotive applications. RISC-V is gaining traction, and open-source hardware (OSH) platforms offer solutions to issues such as IP costs and vendor dependency. Existing multi-core cache-coherent RISC-V platforms are complex and not efficient for small embedded core clusters. We propose an open-source SystemVerilog implementation of a lightweight snoop-based cache-coherent cluster of Linux-capable CVA6 cores. Our design uses the MOESI protocol via the Arm's AMBA ACE protocol. Evaluated with S"},"verification_status":{"content_addressed":true,"pith_receipt":true,"author_attested":false,"weak_author_claims":0,"strong_author_claims":0,"externally_anchored":false,"storage_verified":false,"citation_signatures":0,"replication_records":0,"graph_snapshot":true,"references_resolved":false,"formal_links_present":false},"canonical_record":{"source":{"id":"2407.19895","kind":"arxiv","version":2},"metadata":{"license":"http://arxiv.org/licenses/nonexclusive-distrib/1.0/","primary_cat":"eess.SY","submitted_at":"2024-07-29T11:17:26Z","cross_cats_sorted":["cs.SY"],"title_canon_sha256":"fbbc2a28be1b11baed79d07a9a79e5d30ae74d77ac6c4458a78b5f9de4870b22","abstract_canon_sha256":"9e329ba33f423cf8e591e48514a362399bd8007b402eb99fa0fe93a652c08881"},"schema_version":"1.0"},"receipt":{"kind":"pith_receipt","key_id":"pith-v1-2026-05","algorithm":"ed25519","signed_at":"2026-07-05T08:54:16.192066Z","signature_b64":"WoqoJxIV+BsM2+OjDiKDoN8EHsK1Sohv8yYmzCeh5MBleskPNaBzgmhOIk3kIBhCR+HyqApSmSji2WNS8hZvAw==","signed_message":"canonical_sha256_bytes","builder_version":"pith-number-builder-2026-05-17-v1","receipt_version":"0.3","canonical_sha256":"095570dce09aedf8cf8d49895b32a00a896c7399d3248131a4898c9ebeabb674","last_reissued_at":"2026-07-05T08:54:16.191530Z","signature_status":"signed_v1","first_computed_at":"2026-07-05T08:54:16.191530Z","public_key_fingerprint":"8d4b5ee74e4693bcd1df2446408b0d54"},"graph_snapshot":{"paper":{"title":"Culsans: An Efficient Snoop-based Coherency Unit for the CVA6 Open Source RISC-V application processor","license":"http://arxiv.org/licenses/nonexclusive-distrib/1.0/","headline":"","cross_cats":["cs.SY"],"primary_cat":"eess.SY","authors_text":"Abdul Basit Sajjad, Davide Rossi, Enrico Zelioli, Gianmarco Ottavi, Luca Benini, Luca Valente, Massimiliano Giacometti, Nils Wistoff, Riccardo Tedeschi","submitted_at":"2024-07-29T11:17:26Z","abstract_excerpt":"Symmetric Multi-Processing (SMP) based on cache coherency is crucial for high-end embedded systems like automotive applications. RISC-V is gaining traction, and open-source hardware (OSH) platforms offer solutions to issues such as IP costs and vendor dependency. Existing multi-core cache-coherent RISC-V platforms are complex and not efficient for small embedded core clusters. We propose an open-source SystemVerilog implementation of a lightweight snoop-based cache-coherent cluster of Linux-capable CVA6 cores. Our design uses the MOESI protocol via the Arm's AMBA ACE protocol. Evaluated with S"},"claims":{"count":0,"items":[],"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"source":{"id":"2407.19895","kind":"arxiv","version":2},"verdict":{"id":null,"model_set":{},"created_at":null,"strongest_claim":"","one_line_summary":"","pipeline_version":null,"weakest_assumption":"","pith_extraction_headline":""},"integrity":{"clean":true,"summary":{"advisory":0,"critical":0,"by_detector":{},"informational":0},"endpoint":"/pith/2407.19895/integrity.json","findings":[],"available":true,"detectors_run":[],"snapshot_sha256":"c28c3603d3b5d939e8dc4c7e95fa8dfce3d595e45f758748cecf8e644a296938"},"references":{"count":0,"sample":[],"resolved_work":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57","internal_anchors":0},"formal_canon":{"evidence_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"author_claims":{"count":0,"strong_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"builder_version":"pith-number-builder-2026-05-17-v1"},"aliases":[{"alias_kind":"arxiv","alias_value":"2407.19895","created_at":"2026-07-05T08:54:16.191593+00:00"},{"alias_kind":"arxiv_version","alias_value":"2407.19895v2","created_at":"2026-07-05T08:54:16.191593+00:00"},{"alias_kind":"doi","alias_value":"10.48550/arxiv.2407.19895","created_at":"2026-07-05T08:54:16.191593+00:00"},{"alias_kind":"pith_short_12","alias_value":"BFKXBXHATLW7","created_at":"2026-07-05T08:54:16.191593+00:00"},{"alias_kind":"pith_short_16","alias_value":"BFKXBXHATLW7RT4N","created_at":"2026-07-05T08:54:16.191593+00:00"},{"alias_kind":"pith_short_8","alias_value":"BFKXBXHA","created_at":"2026-07-05T08:54:16.191593+00:00"}],"events":[],"event_summary":{},"paper_claims":[],"inbound_citations":{"count":1,"internal_anchor_count":1,"sample":[{"citing_arxiv_id":"2608.04247","citing_title":"A Centralized Performance Monitoring Architecture for Heterogeneous Multicore SoCs","ref_index":82,"is_internal_anchor":true}]},"formal_canon":{"evidence_count":0,"sample":[],"anchors":[]},"links":{"html":"https://pith.science/pith/BFKXBXHATLW7RT4NJGEVWMVABK","json":"https://pith.science/pith/BFKXBXHATLW7RT4NJGEVWMVABK.json","graph_json":"https://pith.science/api/pith-number/BFKXBXHATLW7RT4NJGEVWMVABK/graph.json","events_json":"https://pith.science/api/pith-number/BFKXBXHATLW7RT4NJGEVWMVABK/events.json","paper":"https://pith.science/paper/BFKXBXHA"},"agent_actions":{"view_html":"https://pith.science/pith/BFKXBXHATLW7RT4NJGEVWMVABK","download_json":"https://pith.science/pith/BFKXBXHATLW7RT4NJGEVWMVABK.json","view_paper":"https://pith.science/paper/BFKXBXHA","resolve_alias":"https://pith.science/api/pith-number/resolve?arxiv=2407.19895&json=true","fetch_graph":"https://pith.science/api/pith-number/BFKXBXHATLW7RT4NJGEVWMVABK/graph.json","fetch_events":"https://pith.science/api/pith-number/BFKXBXHATLW7RT4NJGEVWMVABK/events.json","actions":{"anchor_timestamp":"https://pith.science/pith/BFKXBXHATLW7RT4NJGEVWMVABK/action/timestamp_anchor","attest_storage":"https://pith.science/pith/BFKXBXHATLW7RT4NJGEVWMVABK/action/storage_attestation","attest_author":"https://pith.science/pith/BFKXBXHATLW7RT4NJGEVWMVABK/action/author_attestation","sign_citation":"https://pith.science/pith/BFKXBXHATLW7RT4NJGEVWMVABK/action/citation_signature","submit_replication":"https://pith.science/pith/BFKXBXHATLW7RT4NJGEVWMVABK/action/replication_record"}},"created_at":"2026-07-05T08:54:16.191593+00:00","updated_at":"2026-07-05T08:54:16.191593+00:00"}