{"record_type":"pith_number_record","schema_url":"https://pith.science/schemas/pith-number/v1.json","pith_number":"pith:2025:DMFG36R7RO4DCXHYVU5RLM6KEJ","short_pith_number":"pith:DMFG36R7","schema_version":"1.0","canonical_sha256":"1b0a6dfa3f8bb8315cf8ad3b15b3ca22721c427988d6f3d4c5b57e5aba50cf37","source":{"kind":"arxiv","id":"2508.19299","version":1},"attestation_state":"computed","paper":{"title":"OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs","license":"http://creativecommons.org/licenses/by/4.0/","headline":"","cross_cats":["cs.PF"],"primary_cat":"cs.AR","authors_text":"Cong Hao, Rishov Sarkar","submitted_at":"2025-08-25T18:24:09Z","abstract_excerpt":"High-Level Synthesis (HLS) is increasingly popular for hardware design using C/C++ instead of Register-Transfer Level (RTL). To express concurrent hardware behavior in a sequential language like C/C++, HLS tools introduce constructs such as infinite loops and dataflow modules connected by FIFOs. However, efficiently and accurately simulating these constructs at C level remains challenging. First, without hardware timing information, functional verification typically requires slow RTL synthesis and simulation, as the current approaches in commercial HLS tools. Second, cycle-accurate performance"},"verification_status":{"content_addressed":true,"pith_receipt":true,"author_attested":false,"weak_author_claims":0,"strong_author_claims":0,"externally_anchored":false,"storage_verified":false,"citation_signatures":0,"replication_records":0,"graph_snapshot":true,"references_resolved":false,"formal_links_present":false},"canonical_record":{"source":{"id":"2508.19299","kind":"arxiv","version":1},"metadata":{"license":"http://creativecommons.org/licenses/by/4.0/","primary_cat":"cs.AR","submitted_at":"2025-08-25T18:24:09Z","cross_cats_sorted":["cs.PF"],"title_canon_sha256":"057bb07934552c5d838dafccfbfee768c28a76fc485f33b70763ac6fde0f7b2f","abstract_canon_sha256":"02a4ad5a89eb7ad708c4af1e2bebb6c0795dbd114776ab8951dd4d1e463494cc"},"schema_version":"1.0"},"receipt":{"kind":"pith_receipt","key_id":"pith-v1-2026-05","algorithm":"ed25519","signed_at":"2026-07-05T11:59:42.770207Z","signature_b64":"3t7Uv3J4qkXx+vmTzDV/xpnCzaeydUucHOmfQKIBgJUePBfewg2bJOgLPUuSphb5cfOGky814k3OJq27VSixCg==","signed_message":"canonical_sha256_bytes","builder_version":"pith-number-builder-2026-05-17-v1","receipt_version":"0.3","canonical_sha256":"1b0a6dfa3f8bb8315cf8ad3b15b3ca22721c427988d6f3d4c5b57e5aba50cf37","last_reissued_at":"2026-07-05T11:59:42.769715Z","signature_status":"signed_v1","first_computed_at":"2026-07-05T11:59:42.769715Z","public_key_fingerprint":"8d4b5ee74e4693bcd1df2446408b0d54"},"graph_snapshot":{"paper":{"title":"OmniSim: Simulating Hardware with C Speed and RTL Accuracy for High-Level Synthesis Designs","license":"http://creativecommons.org/licenses/by/4.0/","headline":"","cross_cats":["cs.PF"],"primary_cat":"cs.AR","authors_text":"Cong Hao, Rishov Sarkar","submitted_at":"2025-08-25T18:24:09Z","abstract_excerpt":"High-Level Synthesis (HLS) is increasingly popular for hardware design using C/C++ instead of Register-Transfer Level (RTL). To express concurrent hardware behavior in a sequential language like C/C++, HLS tools introduce constructs such as infinite loops and dataflow modules connected by FIFOs. However, efficiently and accurately simulating these constructs at C level remains challenging. First, without hardware timing information, functional verification typically requires slow RTL synthesis and simulation, as the current approaches in commercial HLS tools. Second, cycle-accurate performance"},"claims":{"count":0,"items":[],"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"source":{"id":"2508.19299","kind":"arxiv","version":1},"verdict":{"id":null,"model_set":{},"created_at":null,"strongest_claim":"","one_line_summary":"","pipeline_version":null,"weakest_assumption":"","pith_extraction_headline":""},"integrity":{"clean":true,"summary":{"advisory":0,"critical":0,"by_detector":{},"informational":0},"endpoint":"/pith/2508.19299/integrity.json","findings":[],"available":true,"detectors_run":[],"snapshot_sha256":"c28c3603d3b5d939e8dc4c7e95fa8dfce3d595e45f758748cecf8e644a296938"},"references":{"count":0,"sample":[],"resolved_work":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57","internal_anchors":0},"formal_canon":{"evidence_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"author_claims":{"count":0,"strong_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"builder_version":"pith-number-builder-2026-05-17-v1"},"aliases":[{"alias_kind":"arxiv","alias_value":"2508.19299","created_at":"2026-07-05T11:59:42.769771+00:00"},{"alias_kind":"arxiv_version","alias_value":"2508.19299v1","created_at":"2026-07-05T11:59:42.769771+00:00"},{"alias_kind":"doi","alias_value":"10.48550/arxiv.2508.19299","created_at":"2026-07-05T11:59:42.769771+00:00"},{"alias_kind":"pith_short_12","alias_value":"DMFG36R7RO4D","created_at":"2026-07-05T11:59:42.769771+00:00"},{"alias_kind":"pith_short_16","alias_value":"DMFG36R7RO4DCXHY","created_at":"2026-07-05T11:59:42.769771+00:00"},{"alias_kind":"pith_short_8","alias_value":"DMFG36R7","created_at":"2026-07-05T11:59:42.769771+00:00"}],"events":[],"event_summary":{},"paper_claims":[],"inbound_citations":{"count":1,"internal_anchor_count":1,"sample":[{"citing_arxiv_id":"2508.19293","citing_title":"Three-Dimensional Continuous Multi-Walled Carbon Nanotubes Network-Toughened Diamond Composite","ref_index":21,"is_internal_anchor":true}]},"formal_canon":{"evidence_count":0,"sample":[],"anchors":[]},"links":{"html":"https://pith.science/pith/DMFG36R7RO4DCXHYVU5RLM6KEJ","json":"https://pith.science/pith/DMFG36R7RO4DCXHYVU5RLM6KEJ.json","graph_json":"https://pith.science/api/pith-number/DMFG36R7RO4DCXHYVU5RLM6KEJ/graph.json","events_json":"https://pith.science/api/pith-number/DMFG36R7RO4DCXHYVU5RLM6KEJ/events.json","paper":"https://pith.science/paper/DMFG36R7"},"agent_actions":{"view_html":"https://pith.science/pith/DMFG36R7RO4DCXHYVU5RLM6KEJ","download_json":"https://pith.science/pith/DMFG36R7RO4DCXHYVU5RLM6KEJ.json","view_paper":"https://pith.science/paper/DMFG36R7","resolve_alias":"https://pith.science/api/pith-number/resolve?arxiv=2508.19299&json=true","fetch_graph":"https://pith.science/api/pith-number/DMFG36R7RO4DCXHYVU5RLM6KEJ/graph.json","fetch_events":"https://pith.science/api/pith-number/DMFG36R7RO4DCXHYVU5RLM6KEJ/events.json","actions":{"anchor_timestamp":"https://pith.science/pith/DMFG36R7RO4DCXHYVU5RLM6KEJ/action/timestamp_anchor","attest_storage":"https://pith.science/pith/DMFG36R7RO4DCXHYVU5RLM6KEJ/action/storage_attestation","attest_author":"https://pith.science/pith/DMFG36R7RO4DCXHYVU5RLM6KEJ/action/author_attestation","sign_citation":"https://pith.science/pith/DMFG36R7RO4DCXHYVU5RLM6KEJ/action/citation_signature","submit_replication":"https://pith.science/pith/DMFG36R7RO4DCXHYVU5RLM6KEJ/action/replication_record"}},"created_at":"2026-07-05T11:59:42.769771+00:00","updated_at":"2026-07-05T11:59:42.769771+00:00"}