{"record_type":"pith_number_record","schema_url":"https://pith.science/schemas/pith-number/v1.json","pith_number":"pith:2023:DS7O4MD2ROUUQTDP2NVV7ULJO2","short_pith_number":"pith:DS7O4MD2","schema_version":"1.0","canonical_sha256":"1cbeee307a8ba9484c6fd36b5fd1697680898024857dba7aac76597b9be42041","source":{"kind":"arxiv","id":"2307.16123","version":1},"attestation_state":"computed","paper":{"title":"Exploiting Parallel Memory Write Requests for Covert Channel Attacks in Integrated CPU-GPU Systems","license":"http://creativecommons.org/licenses/by/4.0/","headline":"","cross_cats":["cs.AR"],"primary_cat":"cs.CR","authors_text":"Ghadeer Almusaddar, Hoda Naghibijouybari","submitted_at":"2023-07-30T04:07:05Z","abstract_excerpt":"In heterogeneous SoCs, accelerators like integrated GPUs (iGPUs) are integrated on the same chip as CPUs, sharing the memory subsystem. In such systems, the massive memory requests from throughput-oriented accelerators significantly interfere with CPU memory requests. In addition to the large performance impact, this interference provides an attacker with a strong leakage vector for covert attacks across the processors, which is hard to achieve across the cores in a multi-core CPU. In this paper, we demonstrate that parallel memory write requests of the iGPU and more specifically, the manageme"},"verification_status":{"content_addressed":true,"pith_receipt":true,"author_attested":false,"weak_author_claims":0,"strong_author_claims":0,"externally_anchored":false,"storage_verified":false,"citation_signatures":0,"replication_records":0,"graph_snapshot":true,"references_resolved":false,"formal_links_present":false},"canonical_record":{"source":{"id":"2307.16123","kind":"arxiv","version":1},"metadata":{"license":"http://creativecommons.org/licenses/by/4.0/","primary_cat":"cs.CR","submitted_at":"2023-07-30T04:07:05Z","cross_cats_sorted":["cs.AR"],"title_canon_sha256":"95b156578376ad84788af53d36e1e54e34c3ee69a91442d2ce749a54dc76afb7","abstract_canon_sha256":"88c00ab142aa8719d4dd0abbf51672cffd1c9da9c3325088ad528b8fcae169ea"},"schema_version":"1.0"},"receipt":{"kind":"pith_receipt","key_id":"pith-v1-2026-05","algorithm":"ed25519","signed_at":"2026-07-05T06:35:59.013082Z","signature_b64":"uatJ2sUzBCLTb/+p7Gwa8Q2ELN2SIfiByJx5Labi6RNIM/YiVhy0em+8jcSt1P8KTz6SZ3+muENm2qkkmjohCw==","signed_message":"canonical_sha256_bytes","builder_version":"pith-number-builder-2026-05-17-v1","receipt_version":"0.3","canonical_sha256":"1cbeee307a8ba9484c6fd36b5fd1697680898024857dba7aac76597b9be42041","last_reissued_at":"2026-07-05T06:35:59.012633Z","signature_status":"signed_v1","first_computed_at":"2026-07-05T06:35:59.012633Z","public_key_fingerprint":"8d4b5ee74e4693bcd1df2446408b0d54"},"graph_snapshot":{"paper":{"title":"Exploiting Parallel Memory Write Requests for Covert Channel Attacks in Integrated CPU-GPU Systems","license":"http://creativecommons.org/licenses/by/4.0/","headline":"","cross_cats":["cs.AR"],"primary_cat":"cs.CR","authors_text":"Ghadeer Almusaddar, Hoda Naghibijouybari","submitted_at":"2023-07-30T04:07:05Z","abstract_excerpt":"In heterogeneous SoCs, accelerators like integrated GPUs (iGPUs) are integrated on the same chip as CPUs, sharing the memory subsystem. In such systems, the massive memory requests from throughput-oriented accelerators significantly interfere with CPU memory requests. In addition to the large performance impact, this interference provides an attacker with a strong leakage vector for covert attacks across the processors, which is hard to achieve across the cores in a multi-core CPU. In this paper, we demonstrate that parallel memory write requests of the iGPU and more specifically, the manageme"},"claims":{"count":0,"items":[],"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"source":{"id":"2307.16123","kind":"arxiv","version":1},"verdict":{"id":null,"model_set":{},"created_at":null,"strongest_claim":"","one_line_summary":"","pipeline_version":null,"weakest_assumption":"","pith_extraction_headline":""},"integrity":{"clean":true,"summary":{"advisory":0,"critical":0,"by_detector":{},"informational":0},"endpoint":"/pith/2307.16123/integrity.json","findings":[],"available":true,"detectors_run":[],"snapshot_sha256":"c28c3603d3b5d939e8dc4c7e95fa8dfce3d595e45f758748cecf8e644a296938"},"references":{"count":0,"sample":[],"resolved_work":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57","internal_anchors":0},"formal_canon":{"evidence_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"author_claims":{"count":0,"strong_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"builder_version":"pith-number-builder-2026-05-17-v1"},"aliases":[{"alias_kind":"arxiv","alias_value":"2307.16123","created_at":"2026-07-05T06:35:59.012699+00:00"},{"alias_kind":"arxiv_version","alias_value":"2307.16123v1","created_at":"2026-07-05T06:35:59.012699+00:00"},{"alias_kind":"doi","alias_value":"10.48550/arxiv.2307.16123","created_at":"2026-07-05T06:35:59.012699+00:00"},{"alias_kind":"pith_short_12","alias_value":"DS7O4MD2ROUU","created_at":"2026-07-05T06:35:59.012699+00:00"},{"alias_kind":"pith_short_16","alias_value":"DS7O4MD2ROUUQTDP","created_at":"2026-07-05T06:35:59.012699+00:00"},{"alias_kind":"pith_short_8","alias_value":"DS7O4MD2","created_at":"2026-07-05T06:35:59.012699+00:00"}],"events":[],"event_summary":{},"paper_claims":[],"inbound_citations":{"count":1,"internal_anchor_count":1,"sample":[{"citing_arxiv_id":"2504.13385","citing_title":"EXAM: Exploiting Exclusive System-Level Cache in Apple M-Series SoCs for Enhanced Cache Occupancy Attacks","ref_index":1,"is_internal_anchor":true}]},"formal_canon":{"evidence_count":0,"sample":[],"anchors":[]},"links":{"html":"https://pith.science/pith/DS7O4MD2ROUUQTDP2NVV7ULJO2","json":"https://pith.science/pith/DS7O4MD2ROUUQTDP2NVV7ULJO2.json","graph_json":"https://pith.science/api/pith-number/DS7O4MD2ROUUQTDP2NVV7ULJO2/graph.json","events_json":"https://pith.science/api/pith-number/DS7O4MD2ROUUQTDP2NVV7ULJO2/events.json","paper":"https://pith.science/paper/DS7O4MD2"},"agent_actions":{"view_html":"https://pith.science/pith/DS7O4MD2ROUUQTDP2NVV7ULJO2","download_json":"https://pith.science/pith/DS7O4MD2ROUUQTDP2NVV7ULJO2.json","view_paper":"https://pith.science/paper/DS7O4MD2","resolve_alias":"https://pith.science/api/pith-number/resolve?arxiv=2307.16123&json=true","fetch_graph":"https://pith.science/api/pith-number/DS7O4MD2ROUUQTDP2NVV7ULJO2/graph.json","fetch_events":"https://pith.science/api/pith-number/DS7O4MD2ROUUQTDP2NVV7ULJO2/events.json","actions":{"anchor_timestamp":"https://pith.science/pith/DS7O4MD2ROUUQTDP2NVV7ULJO2/action/timestamp_anchor","attest_storage":"https://pith.science/pith/DS7O4MD2ROUUQTDP2NVV7ULJO2/action/storage_attestation","attest_author":"https://pith.science/pith/DS7O4MD2ROUUQTDP2NVV7ULJO2/action/author_attestation","sign_citation":"https://pith.science/pith/DS7O4MD2ROUUQTDP2NVV7ULJO2/action/citation_signature","submit_replication":"https://pith.science/pith/DS7O4MD2ROUUQTDP2NVV7ULJO2/action/replication_record"}},"created_at":"2026-07-05T06:35:59.012699+00:00","updated_at":"2026-07-05T06:35:59.012699+00:00"}