{"record_type":"pith_number_record","schema_url":"https://pith.science/schemas/pith-number/v1.json","pith_number":"pith:2024:H36XR36BCRWJIMJFLIWKSFH4VS","short_pith_number":"pith:H36XR36B","schema_version":"1.0","canonical_sha256":"3efd78efc1146c9431255a2ca914fcacb701cd4e9bdd9018c8dc0f63724227e8","source":{"kind":"arxiv","id":"2409.08141","version":3},"attestation_state":"computed","paper":{"title":"Rethinking Programmed I/O for Fast Devices, Cheap Cores, and Coherent Interconnects","license":"http://arxiv.org/licenses/nonexclusive-distrib/1.0/","headline":"","cross_cats":["cs.OS"],"primary_cat":"cs.AR","authors_text":"Anastasiia Ruzhanskaia, David Cock, Pengcheng Xu, Timothy Roscoe","submitted_at":"2024-09-12T15:34:23Z","abstract_excerpt":"Conventional wisdom holds that an efficient interface between an OS running on a CPU and a high-bandwidth I/O device should use Direct Memory Access (DMA) to offload data transfer, descriptor rings for buffering and queuing, and interrupts for asynchrony between cores and device.\n  In this paper we question this wisdom in the light of two trends: modern and emerging cache-coherent interconnects like CXL3.0, and workloads, particularly microservices and serverless computing. Like some others before us, we argue that the assumptions of the DMA-based model are obsolete, and in many use-cases prog"},"verification_status":{"content_addressed":true,"pith_receipt":true,"author_attested":false,"weak_author_claims":0,"strong_author_claims":0,"externally_anchored":false,"storage_verified":false,"citation_signatures":0,"replication_records":0,"graph_snapshot":true,"references_resolved":false,"formal_links_present":false},"canonical_record":{"source":{"id":"2409.08141","kind":"arxiv","version":3},"metadata":{"license":"http://arxiv.org/licenses/nonexclusive-distrib/1.0/","primary_cat":"cs.AR","submitted_at":"2024-09-12T15:34:23Z","cross_cats_sorted":["cs.OS"],"title_canon_sha256":"18d4b8f1740ac9e8491e5e29d40d05a073c0cf2a89f46d9b10a71161fb3faa77","abstract_canon_sha256":"8dbfe07d6f6413aa3a03df880061e1f2ef029be93c7e70f3d87117f17c373642"},"schema_version":"1.0"},"receipt":{"kind":"pith_receipt","key_id":"pith-v1-2026-05","algorithm":"ed25519","signed_at":"2026-07-05T10:53:11.690002Z","signature_b64":"t6ql2AEuhnnXfDNhDV4DWxUQ/DRH53COf5x9zrOdQw4PWE53ww/Yzk7UtOOZKvNkrOeG+R9o1fbSsvGU+BxYDA==","signed_message":"canonical_sha256_bytes","builder_version":"pith-number-builder-2026-05-17-v1","receipt_version":"0.3","canonical_sha256":"3efd78efc1146c9431255a2ca914fcacb701cd4e9bdd9018c8dc0f63724227e8","last_reissued_at":"2026-07-05T10:53:11.689479Z","signature_status":"signed_v1","first_computed_at":"2026-07-05T10:53:11.689479Z","public_key_fingerprint":"8d4b5ee74e4693bcd1df2446408b0d54"},"graph_snapshot":{"paper":{"title":"Rethinking Programmed I/O for Fast Devices, Cheap Cores, and Coherent Interconnects","license":"http://arxiv.org/licenses/nonexclusive-distrib/1.0/","headline":"","cross_cats":["cs.OS"],"primary_cat":"cs.AR","authors_text":"Anastasiia Ruzhanskaia, David Cock, Pengcheng Xu, Timothy Roscoe","submitted_at":"2024-09-12T15:34:23Z","abstract_excerpt":"Conventional wisdom holds that an efficient interface between an OS running on a CPU and a high-bandwidth I/O device should use Direct Memory Access (DMA) to offload data transfer, descriptor rings for buffering and queuing, and interrupts for asynchrony between cores and device.\n  In this paper we question this wisdom in the light of two trends: modern and emerging cache-coherent interconnects like CXL3.0, and workloads, particularly microservices and serverless computing. Like some others before us, we argue that the assumptions of the DMA-based model are obsolete, and in many use-cases prog"},"claims":{"count":0,"items":[],"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"source":{"id":"2409.08141","kind":"arxiv","version":3},"verdict":{"id":null,"model_set":{},"created_at":null,"strongest_claim":"","one_line_summary":"","pipeline_version":null,"weakest_assumption":"","pith_extraction_headline":""},"integrity":{"clean":true,"summary":{"advisory":0,"critical":0,"by_detector":{},"informational":0},"endpoint":"/pith/2409.08141/integrity.json","findings":[],"available":true,"detectors_run":[],"snapshot_sha256":"c28c3603d3b5d939e8dc4c7e95fa8dfce3d595e45f758748cecf8e644a296938"},"references":{"count":0,"sample":[],"resolved_work":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57","internal_anchors":0},"formal_canon":{"evidence_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"author_claims":{"count":0,"strong_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"builder_version":"pith-number-builder-2026-05-17-v1"},"aliases":[{"alias_kind":"arxiv","alias_value":"2409.08141","created_at":"2026-07-05T10:53:11.689539+00:00"},{"alias_kind":"arxiv_version","alias_value":"2409.08141v3","created_at":"2026-07-05T10:53:11.689539+00:00"},{"alias_kind":"doi","alias_value":"10.48550/arxiv.2409.08141","created_at":"2026-07-05T10:53:11.689539+00:00"},{"alias_kind":"pith_short_12","alias_value":"H36XR36BCRWJ","created_at":"2026-07-05T10:53:11.689539+00:00"},{"alias_kind":"pith_short_16","alias_value":"H36XR36BCRWJIMJF","created_at":"2026-07-05T10:53:11.689539+00:00"},{"alias_kind":"pith_short_8","alias_value":"H36XR36B","created_at":"2026-07-05T10:53:11.689539+00:00"}],"events":[],"event_summary":{},"paper_claims":[],"inbound_citations":{"count":1,"internal_anchor_count":1,"sample":[{"citing_arxiv_id":"2506.09758","citing_title":"Mainframe-Style Channel Controllers for Modern Disaggregated Memory Systems","ref_index":47,"is_internal_anchor":true}]},"formal_canon":{"evidence_count":0,"sample":[],"anchors":[]},"links":{"html":"https://pith.science/pith/H36XR36BCRWJIMJFLIWKSFH4VS","json":"https://pith.science/pith/H36XR36BCRWJIMJFLIWKSFH4VS.json","graph_json":"https://pith.science/api/pith-number/H36XR36BCRWJIMJFLIWKSFH4VS/graph.json","events_json":"https://pith.science/api/pith-number/H36XR36BCRWJIMJFLIWKSFH4VS/events.json","paper":"https://pith.science/paper/H36XR36B"},"agent_actions":{"view_html":"https://pith.science/pith/H36XR36BCRWJIMJFLIWKSFH4VS","download_json":"https://pith.science/pith/H36XR36BCRWJIMJFLIWKSFH4VS.json","view_paper":"https://pith.science/paper/H36XR36B","resolve_alias":"https://pith.science/api/pith-number/resolve?arxiv=2409.08141&json=true","fetch_graph":"https://pith.science/api/pith-number/H36XR36BCRWJIMJFLIWKSFH4VS/graph.json","fetch_events":"https://pith.science/api/pith-number/H36XR36BCRWJIMJFLIWKSFH4VS/events.json","actions":{"anchor_timestamp":"https://pith.science/pith/H36XR36BCRWJIMJFLIWKSFH4VS/action/timestamp_anchor","attest_storage":"https://pith.science/pith/H36XR36BCRWJIMJFLIWKSFH4VS/action/storage_attestation","attest_author":"https://pith.science/pith/H36XR36BCRWJIMJFLIWKSFH4VS/action/author_attestation","sign_citation":"https://pith.science/pith/H36XR36BCRWJIMJFLIWKSFH4VS/action/citation_signature","submit_replication":"https://pith.science/pith/H36XR36BCRWJIMJFLIWKSFH4VS/action/replication_record"}},"created_at":"2026-07-05T10:53:11.689539+00:00","updated_at":"2026-07-05T10:53:11.689539+00:00"}