{"record_type":"pith_number_record","schema_url":"https://pith.science/schemas/pith-number/v1.json","pith_number":"pith:2024:OASP5TQCDPF3HRMWPODUJLRKNE","short_pith_number":"pith:OASP5TQC","schema_version":"1.0","canonical_sha256":"7024fece021bcbb3c5967b8744ae2a6910b9d559551ec8c2360ee89f145cfc9b","source":{"kind":"arxiv","id":"2408.08927","version":2},"attestation_state":"computed","paper":{"title":"VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool","license":"http://creativecommons.org/licenses/by/4.0/","headline":"","cross_cats":["cs.CL"],"primary_cat":"cs.AI","authors_text":"Brucek Khailany, Chia-Tung Ho, Haoxing Ren","submitted_at":"2024-08-15T20:06:06Z","abstract_excerpt":"Due to the growing complexity of modern Integrated Circuits (ICs), automating hardware design can prevent a significant amount of human error from the engineering process and result in less errors. Verilog is a popular hardware description language for designing and modeling digital systems; thus, Verilog generation is one of the emerging areas of research to facilitate the design process. In this work, we propose VerilogCoder, a system of multiple Artificial Intelligence (AI) agents for Verilog code generation, to autonomously write Verilog code and fix syntax and functional errors using coll"},"verification_status":{"content_addressed":true,"pith_receipt":true,"author_attested":false,"weak_author_claims":0,"strong_author_claims":0,"externally_anchored":false,"storage_verified":false,"citation_signatures":0,"replication_records":0,"graph_snapshot":true,"references_resolved":false,"formal_links_present":false},"canonical_record":{"source":{"id":"2408.08927","kind":"arxiv","version":2},"metadata":{"license":"http://creativecommons.org/licenses/by/4.0/","primary_cat":"cs.AI","submitted_at":"2024-08-15T20:06:06Z","cross_cats_sorted":["cs.CL"],"title_canon_sha256":"cae94d306ee5d449e0262e22bb0a376d0667943776050a698ae685a745cd2dcf","abstract_canon_sha256":"fe9a2a46fdc189f100799fa3ee9c4cba7a5476bf53ee5fe06e6d6cc5cfa2f3d0"},"schema_version":"1.0"},"receipt":{"kind":"pith_receipt","key_id":"pith-v1-2026-05","algorithm":"ed25519","signed_at":"2026-07-05T10:24:24.133389Z","signature_b64":"BlMKFYDi7SmuViZK3OenkeLDFJETsMASMmXMVRzpvmtn1V1e1JU49MVhmv3cOeYZv++t8tjySexJ3mM0rIwbCg==","signed_message":"canonical_sha256_bytes","builder_version":"pith-number-builder-2026-05-17-v1","receipt_version":"0.3","canonical_sha256":"7024fece021bcbb3c5967b8744ae2a6910b9d559551ec8c2360ee89f145cfc9b","last_reissued_at":"2026-07-05T10:24:24.132826Z","signature_status":"signed_v1","first_computed_at":"2026-07-05T10:24:24.132826Z","public_key_fingerprint":"8d4b5ee74e4693bcd1df2446408b0d54"},"graph_snapshot":{"paper":{"title":"VerilogCoder: Autonomous Verilog Coding Agents with Graph-based Planning and Abstract Syntax Tree (AST)-based Waveform Tracing Tool","license":"http://creativecommons.org/licenses/by/4.0/","headline":"","cross_cats":["cs.CL"],"primary_cat":"cs.AI","authors_text":"Brucek Khailany, Chia-Tung Ho, Haoxing Ren","submitted_at":"2024-08-15T20:06:06Z","abstract_excerpt":"Due to the growing complexity of modern Integrated Circuits (ICs), automating hardware design can prevent a significant amount of human error from the engineering process and result in less errors. Verilog is a popular hardware description language for designing and modeling digital systems; thus, Verilog generation is one of the emerging areas of research to facilitate the design process. In this work, we propose VerilogCoder, a system of multiple Artificial Intelligence (AI) agents for Verilog code generation, to autonomously write Verilog code and fix syntax and functional errors using coll"},"claims":{"count":0,"items":[],"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"source":{"id":"2408.08927","kind":"arxiv","version":2},"verdict":{"id":null,"model_set":{},"created_at":null,"strongest_claim":"","one_line_summary":"","pipeline_version":null,"weakest_assumption":"","pith_extraction_headline":""},"integrity":{"clean":true,"summary":{"advisory":0,"critical":0,"by_detector":{},"informational":0},"endpoint":"/pith/2408.08927/integrity.json","findings":[],"available":true,"detectors_run":[],"snapshot_sha256":"c28c3603d3b5d939e8dc4c7e95fa8dfce3d595e45f758748cecf8e644a296938"},"references":{"count":0,"sample":[],"resolved_work":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57","internal_anchors":0},"formal_canon":{"evidence_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"author_claims":{"count":0,"strong_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"builder_version":"pith-number-builder-2026-05-17-v1"},"aliases":[{"alias_kind":"arxiv","alias_value":"2408.08927","created_at":"2026-07-05T10:24:24.132891+00:00"},{"alias_kind":"arxiv_version","alias_value":"2408.08927v2","created_at":"2026-07-05T10:24:24.132891+00:00"},{"alias_kind":"doi","alias_value":"10.48550/arxiv.2408.08927","created_at":"2026-07-05T10:24:24.132891+00:00"},{"alias_kind":"pith_short_12","alias_value":"OASP5TQCDPF3","created_at":"2026-07-05T10:24:24.132891+00:00"},{"alias_kind":"pith_short_16","alias_value":"OASP5TQCDPF3HRMW","created_at":"2026-07-05T10:24:24.132891+00:00"},{"alias_kind":"pith_short_8","alias_value":"OASP5TQC","created_at":"2026-07-05T10:24:24.132891+00:00"}],"events":[],"event_summary":{},"paper_claims":[],"inbound_citations":{"count":6,"internal_anchor_count":1,"sample":[{"citing_arxiv_id":"2607.05915","citing_title":"PCBWorld: A Benchmark Environment for Engine-Grounded PCB Design Automation","ref_index":26,"is_internal_anchor":true},{"citing_arxiv_id":"2606.08976","citing_title":"RTL-BenchLS: A Large-Scale Benchmark for RTL Reasoning and Generation with Large Language Models","ref_index":12,"is_internal_anchor":false},{"citing_arxiv_id":"2606.28279","citing_title":"Agentic Hardware Design as Repository-Level Code Evolution","ref_index":16,"is_internal_anchor":false},{"citing_arxiv_id":"2605.15537","citing_title":"RTL-BenchMT: Dynamic Maintenance of RTL Generation Benchmark Through Agent-Assisted Analysis and Revision","ref_index":5,"is_internal_anchor":false},{"citing_arxiv_id":"2604.18162","citing_title":"VerilogCL: A Contrastive Learning Framework for Robust LLM-Based Verilog Generation","ref_index":15,"is_internal_anchor":false},{"citing_arxiv_id":"2604.05963","citing_title":"QiMeng-PRepair: Precise Code Repair via Edit-Aware Reward Optimization","ref_index":3,"is_internal_anchor":false}]},"formal_canon":{"evidence_count":0,"sample":[],"anchors":[]},"links":{"html":"https://pith.science/pith/OASP5TQCDPF3HRMWPODUJLRKNE","json":"https://pith.science/pith/OASP5TQCDPF3HRMWPODUJLRKNE.json","graph_json":"https://pith.science/api/pith-number/OASP5TQCDPF3HRMWPODUJLRKNE/graph.json","events_json":"https://pith.science/api/pith-number/OASP5TQCDPF3HRMWPODUJLRKNE/events.json","paper":"https://pith.science/paper/OASP5TQC"},"agent_actions":{"view_html":"https://pith.science/pith/OASP5TQCDPF3HRMWPODUJLRKNE","download_json":"https://pith.science/pith/OASP5TQCDPF3HRMWPODUJLRKNE.json","view_paper":"https://pith.science/paper/OASP5TQC","resolve_alias":"https://pith.science/api/pith-number/resolve?arxiv=2408.08927&json=true","fetch_graph":"https://pith.science/api/pith-number/OASP5TQCDPF3HRMWPODUJLRKNE/graph.json","fetch_events":"https://pith.science/api/pith-number/OASP5TQCDPF3HRMWPODUJLRKNE/events.json","actions":{"anchor_timestamp":"https://pith.science/pith/OASP5TQCDPF3HRMWPODUJLRKNE/action/timestamp_anchor","attest_storage":"https://pith.science/pith/OASP5TQCDPF3HRMWPODUJLRKNE/action/storage_attestation","attest_author":"https://pith.science/pith/OASP5TQCDPF3HRMWPODUJLRKNE/action/author_attestation","sign_citation":"https://pith.science/pith/OASP5TQCDPF3HRMWPODUJLRKNE/action/citation_signature","submit_replication":"https://pith.science/pith/OASP5TQCDPF3HRMWPODUJLRKNE/action/replication_record"}},"created_at":"2026-07-05T10:24:24.132891+00:00","updated_at":"2026-07-05T10:24:24.132891+00:00"}