{"record_type":"pith_number_record","schema_url":"https://pith.science/schemas/pith-number/v1.json","pith_number":"pith:2023:QTQUXNNZJDJ66FFFCLHCHNM76R","short_pith_number":"pith:QTQUXNNZ","schema_version":"1.0","canonical_sha256":"84e14bb5b948d3ef14a512ce23b59ff4740c39ad40f3129796ada1762f28c17a","source":{"kind":"arxiv","id":"2311.00176","version":5},"attestation_state":"computed","paper":{"title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","license":"http://creativecommons.org/licenses/by/4.0/","headline":"","cross_cats":[],"primary_cat":"cs.CL","authors_text":"Ambar Sarkar, Ankit Jindal, Arjun Chaudhuri, Bill Dally, Bonita Bhaskaran, Brucek Khailany, Bryan Catanzaro, Charley Lind, Chris Cheng, Eric Hill, George Kokai, Ghasem Pasandi, Hanfei Sun, Hao Liu, Haoxing Ren, Himyanshu Anand, Ismet Bayraktaroglu, Jiashang Hu, Jonah Alben, Jonathan Raiman, Kaizhe Xu, Kishor Kunal, Laura Dang, Mingjie Liu, Nathaniel Pinckney, Parikshit Deshpande, Pratik P Suthar, Robert Kirby, Rongjian Liang, Sameer Halepete, Sanmitra Banerjee, Sharon Clay, Siddhanth Dhodhi, Sreedhar Pratty, Stuart Oberman, Sujeet Omar, Sumit Jain, Teodor-Dumitru Ene, Varun Tej, Walker Turner, Xiaowei Li, Zhengjiang Shao","submitted_at":"2023-10-31T22:35:58Z","abstract_excerpt":"ChipNeMo aims to explore the applications of large language models (LLMs) for industrial chip design. Instead of directly deploying off-the-shelf commercial or open-source LLMs, we instead adopt the following domain adaptation techniques: domain-adaptive tokenization, domain-adaptive continued pretraining, model alignment with domain-specific instructions, and domain-adapted retrieval models. We evaluate these methods on three selected LLM applications for chip design: an engineering assistant chatbot, EDA script generation, and bug summarization and analysis. Our evaluations demonstrate that "},"verification_status":{"content_addressed":true,"pith_receipt":true,"author_attested":false,"weak_author_claims":0,"strong_author_claims":0,"externally_anchored":false,"storage_verified":false,"citation_signatures":0,"replication_records":0,"graph_snapshot":true,"references_resolved":false,"formal_links_present":false},"canonical_record":{"source":{"id":"2311.00176","kind":"arxiv","version":5},"metadata":{"license":"http://creativecommons.org/licenses/by/4.0/","primary_cat":"cs.CL","submitted_at":"2023-10-31T22:35:58Z","cross_cats_sorted":[],"title_canon_sha256":"3c0a3034af9a832258e8809a97cfb1e8303a160a27ed7d7b1f365ab97f9ad32b","abstract_canon_sha256":"3c4a595f0a201439959e3a22b19998fb78d9811566f9d6a1441892101d3e457f"},"schema_version":"1.0"},"receipt":{"kind":"pith_receipt","key_id":"pith-v1-2026-05","algorithm":"ed25519","signed_at":"2026-07-05T08:04:35.040690Z","signature_b64":"uME6QH4pV0ngnnRBtbjYhE9P9+cg2KmGxv6GD9gpnfCQdBWmYVePzzSIl1U2dBMj9iaKfVK338u3knLZbeR4DQ==","signed_message":"canonical_sha256_bytes","builder_version":"pith-number-builder-2026-05-17-v1","receipt_version":"0.3","canonical_sha256":"84e14bb5b948d3ef14a512ce23b59ff4740c39ad40f3129796ada1762f28c17a","last_reissued_at":"2026-07-05T08:04:35.040185Z","signature_status":"signed_v1","first_computed_at":"2026-07-05T08:04:35.040185Z","public_key_fingerprint":"8d4b5ee74e4693bcd1df2446408b0d54"},"graph_snapshot":{"paper":{"title":"ChipNeMo: Domain-Adapted LLMs for Chip Design","license":"http://creativecommons.org/licenses/by/4.0/","headline":"","cross_cats":[],"primary_cat":"cs.CL","authors_text":"Ambar Sarkar, Ankit Jindal, Arjun Chaudhuri, Bill Dally, Bonita Bhaskaran, Brucek Khailany, Bryan Catanzaro, Charley Lind, Chris Cheng, Eric Hill, George Kokai, Ghasem Pasandi, Hanfei Sun, Hao Liu, Haoxing Ren, Himyanshu Anand, Ismet Bayraktaroglu, Jiashang Hu, Jonah Alben, Jonathan Raiman, Kaizhe Xu, Kishor Kunal, Laura Dang, Mingjie Liu, Nathaniel Pinckney, Parikshit Deshpande, Pratik P Suthar, Robert Kirby, Rongjian Liang, Sameer Halepete, Sanmitra Banerjee, Sharon Clay, Siddhanth Dhodhi, Sreedhar Pratty, Stuart Oberman, Sujeet Omar, Sumit Jain, Teodor-Dumitru Ene, Varun Tej, Walker Turner, Xiaowei Li, Zhengjiang Shao","submitted_at":"2023-10-31T22:35:58Z","abstract_excerpt":"ChipNeMo aims to explore the applications of large language models (LLMs) for industrial chip design. Instead of directly deploying off-the-shelf commercial or open-source LLMs, we instead adopt the following domain adaptation techniques: domain-adaptive tokenization, domain-adaptive continued pretraining, model alignment with domain-specific instructions, and domain-adapted retrieval models. We evaluate these methods on three selected LLM applications for chip design: an engineering assistant chatbot, EDA script generation, and bug summarization and analysis. Our evaluations demonstrate that "},"claims":{"count":0,"items":[],"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"source":{"id":"2311.00176","kind":"arxiv","version":5},"verdict":{"id":null,"model_set":{},"created_at":null,"strongest_claim":"","one_line_summary":"","pipeline_version":null,"weakest_assumption":"","pith_extraction_headline":""},"integrity":{"clean":true,"summary":{"advisory":0,"critical":0,"by_detector":{},"informational":0},"endpoint":"/pith/2311.00176/integrity.json","findings":[],"available":true,"detectors_run":[],"snapshot_sha256":"c28c3603d3b5d939e8dc4c7e95fa8dfce3d595e45f758748cecf8e644a296938"},"references":{"count":0,"sample":[],"resolved_work":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57","internal_anchors":0},"formal_canon":{"evidence_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"author_claims":{"count":0,"strong_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"builder_version":"pith-number-builder-2026-05-17-v1"},"aliases":[{"alias_kind":"arxiv","alias_value":"2311.00176","created_at":"2026-07-05T08:04:35.040251+00:00"},{"alias_kind":"arxiv_version","alias_value":"2311.00176v5","created_at":"2026-07-05T08:04:35.040251+00:00"},{"alias_kind":"doi","alias_value":"10.48550/arxiv.2311.00176","created_at":"2026-07-05T08:04:35.040251+00:00"},{"alias_kind":"pith_short_12","alias_value":"QTQUXNNZJDJ6","created_at":"2026-07-05T08:04:35.040251+00:00"},{"alias_kind":"pith_short_16","alias_value":"QTQUXNNZJDJ66FFF","created_at":"2026-07-05T08:04:35.040251+00:00"},{"alias_kind":"pith_short_8","alias_value":"QTQUXNNZ","created_at":"2026-07-05T08:04:35.040251+00:00"}],"events":[],"event_summary":{},"paper_claims":[],"inbound_citations":{"count":26,"internal_anchor_count":2,"sample":[{"citing_arxiv_id":"2607.05915","citing_title":"PCBWorld: A Benchmark Environment for Engine-Grounded PCB Design Automation","ref_index":48,"is_internal_anchor":true},{"citing_arxiv_id":"2606.07521","citing_title":"Evaluating Hallucinations in Domain-Adapted Large Language Models","ref_index":11,"is_internal_anchor":true},{"citing_arxiv_id":"2606.21836","citing_title":"AgentDSE: Reasoning-Augmented Architectural Design Space Exploration","ref_index":14,"is_internal_anchor":false},{"citing_arxiv_id":"2606.17253","citing_title":"PDAGENT-BENCH: Characterizing, Grounding, and Architecting LLM Agents for VLSI Physical Design","ref_index":17,"is_internal_anchor":false},{"citing_arxiv_id":"2606.11247","citing_title":"Physics-informed generative AI for semiconductor manufacturing: Enforcing hard physical constraints in generative models by construction","ref_index":30,"is_internal_anchor":false},{"citing_arxiv_id":"2606.05253","citing_title":"Alpha-RTL: Test-Time Training for RTL Hardware Optimization","ref_index":29,"is_internal_anchor":false},{"citing_arxiv_id":"2606.04246","citing_title":"StepPRM-RTL: Stepwise Process-Reward Guided LLM Fine-Tuning for Enhanced RTL Synthesis","ref_index":10,"is_internal_anchor":false},{"citing_arxiv_id":"2605.26498","citing_title":"Verilog-Evolve: Feedback-Driven and Skill-Evolving Verilog Generation","ref_index":4,"is_internal_anchor":false},{"citing_arxiv_id":"2606.12683","citing_title":"From AGI to ASI","ref_index":5,"is_internal_anchor":false},{"citing_arxiv_id":"2605.06936","citing_title":"Bridging the Last Mile of Circuit Design: PostEDA-Bench, a Hierarchical Benchmark for PPA Convergence and DRC Fixing","ref_index":10,"is_internal_anchor":false},{"citing_arxiv_id":"2604.23355","citing_title":"LEGO: An LLM Skill-Based Front-End Design Generation Platform","ref_index":6,"is_internal_anchor":false},{"citing_arxiv_id":"2506.08332","citing_title":"ORFS-agent: Tool-Using Agents for Chip Design Optimization","ref_index":34,"is_internal_anchor":false},{"citing_arxiv_id":"2604.03245","citing_title":"FVRuleLearner: Operator-Level Reasoning Tree (Op-Tree)-Based Rules Learning for Formal Verification","ref_index":8,"is_internal_anchor":false},{"citing_arxiv_id":"2604.27643","citing_title":"HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs","ref_index":10,"is_internal_anchor":false},{"citing_arxiv_id":"2604.27415","citing_title":"ChipLingo: A Systematic Training Framework for Large Language Models in EDA","ref_index":3,"is_internal_anchor":false},{"citing_arxiv_id":"2605.08291","citing_title":"Graph Computation Meets Circuit Algebra: A Task-Aligned Analysis of Graph Neural Networks for Electronic Design Automation","ref_index":76,"is_internal_anchor":false},{"citing_arxiv_id":"2604.24218","citing_title":"RefEvo: Agentic Design with Co-Evolutionary Verification for Agile Reference Model Generation","ref_index":7,"is_internal_anchor":false},{"citing_arxiv_id":"2604.23602","citing_title":"TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog","ref_index":10,"is_internal_anchor":false},{"citing_arxiv_id":"2604.23355","citing_title":"LEGO: An LLM Skill-Based Front-End Design Generation Platform","ref_index":6,"is_internal_anchor":false},{"citing_arxiv_id":"2605.01338","citing_title":"DiagramNet: An End-to-End Recognition Framework and Dataset for Non-Standard System-Level Diagrams","ref_index":13,"is_internal_anchor":false},{"citing_arxiv_id":"2604.18834","citing_title":"Structural Verification for Reliable EDA Code Generation without Tool-in-the-Loop Debugging","ref_index":10,"is_internal_anchor":false},{"citing_arxiv_id":"2604.13523","citing_title":"TensorLift: Automatic Extraction of Tensor-Level ISA Semantics from Accelerator RTL via MLIR Semantic Lifting","ref_index":30,"is_internal_anchor":false},{"citing_arxiv_id":"2605.06936","citing_title":"Bridging the Last Mile of Circuit Design: PostEDA-Bench, a Hierarchical Benchmark for PPA Convergence and DRC Fixing","ref_index":10,"is_internal_anchor":false},{"citing_arxiv_id":"2604.05983","citing_title":"Arch: An AI-Native Hardware Description Language for Register-Transfer Clocked Hardware Design","ref_index":31,"is_internal_anchor":false},{"citing_arxiv_id":"2604.15001","citing_title":"COEVO: Co-Evolutionary Framework for Joint Functional Correctness and PPA Optimization in LLM-Based RTL Generation","ref_index":15,"is_internal_anchor":false}]},"formal_canon":{"evidence_count":0,"sample":[],"anchors":[]},"links":{"html":"https://pith.science/pith/QTQUXNNZJDJ66FFFCLHCHNM76R","json":"https://pith.science/pith/QTQUXNNZJDJ66FFFCLHCHNM76R.json","graph_json":"https://pith.science/api/pith-number/QTQUXNNZJDJ66FFFCLHCHNM76R/graph.json","events_json":"https://pith.science/api/pith-number/QTQUXNNZJDJ66FFFCLHCHNM76R/events.json","paper":"https://pith.science/paper/QTQUXNNZ"},"agent_actions":{"view_html":"https://pith.science/pith/QTQUXNNZJDJ66FFFCLHCHNM76R","download_json":"https://pith.science/pith/QTQUXNNZJDJ66FFFCLHCHNM76R.json","view_paper":"https://pith.science/paper/QTQUXNNZ","resolve_alias":"https://pith.science/api/pith-number/resolve?arxiv=2311.00176&json=true","fetch_graph":"https://pith.science/api/pith-number/QTQUXNNZJDJ66FFFCLHCHNM76R/graph.json","fetch_events":"https://pith.science/api/pith-number/QTQUXNNZJDJ66FFFCLHCHNM76R/events.json","actions":{"anchor_timestamp":"https://pith.science/pith/QTQUXNNZJDJ66FFFCLHCHNM76R/action/timestamp_anchor","attest_storage":"https://pith.science/pith/QTQUXNNZJDJ66FFFCLHCHNM76R/action/storage_attestation","attest_author":"https://pith.science/pith/QTQUXNNZJDJ66FFFCLHCHNM76R/action/author_attestation","sign_citation":"https://pith.science/pith/QTQUXNNZJDJ66FFFCLHCHNM76R/action/citation_signature","submit_replication":"https://pith.science/pith/QTQUXNNZJDJ66FFFCLHCHNM76R/action/replication_record"}},"created_at":"2026-07-05T08:04:35.040251+00:00","updated_at":"2026-07-05T08:04:35.040251+00:00"}