{"record_type":"pith_number_record","schema_url":"https://pith.science/schemas/pith-number/v1.json","pith_number":"pith:2024:R4IBY34MSBMBDVAY7ED4XMRDWJ","short_pith_number":"pith:R4IBY34M","schema_version":"1.0","canonical_sha256":"8f101c6f8c905811d418f907cbb223b26797f66f2e83a9fe09d57eb08a70db80","source":{"kind":"arxiv","id":"2408.04808","version":2},"attestation_state":"computed","paper":{"title":"Scaling Deep Learning Computation over the Inter-Core Connected Intelligence Processor with T10","license":"http://creativecommons.org/licenses/by-nc-sa/4.0/","headline":"","cross_cats":["cs.LG"],"primary_cat":"cs.DC","authors_text":"Jian Huang, Jilong Xue, Lingxiao Ma, Yiqi Liu, Yu Cheng, Yuqi Xue, Ziming Miao","submitted_at":"2024-08-09T01:28:09Z","abstract_excerpt":"As AI chips incorporate numerous parallelized cores to scale deep learning (DL) computing, inter-core communication is enabled recently by employing high-bandwidth and low-latency interconnect links on the chip (e.g., Graphcore IPU). It allows each core to directly access the fast scratchpad memory in other cores, which enables new parallel computing paradigms. However, without proper support for the scalable inter-core connections in current DL compilers, it is hard for developers to exploit the benefits of this new architecture.\n  We present T10, the first DL compiler to exploit the inter-co"},"verification_status":{"content_addressed":true,"pith_receipt":true,"author_attested":false,"weak_author_claims":0,"strong_author_claims":0,"externally_anchored":false,"storage_verified":false,"citation_signatures":0,"replication_records":0,"graph_snapshot":true,"references_resolved":false,"formal_links_present":false},"canonical_record":{"source":{"id":"2408.04808","kind":"arxiv","version":2},"metadata":{"license":"http://creativecommons.org/licenses/by-nc-sa/4.0/","primary_cat":"cs.DC","submitted_at":"2024-08-09T01:28:09Z","cross_cats_sorted":["cs.LG"],"title_canon_sha256":"acb52bceb9f5bcb4b9fce6b3303183ffc3ce2f072ce1f27bb63eb0db1e699104","abstract_canon_sha256":"9b03fce59ae892b5a1ca82301189f827e6eb1f3fccbc8ce06b247136cf38e815"},"schema_version":"1.0"},"receipt":{"kind":"pith_receipt","key_id":"pith-v1-2026-05","algorithm":"ed25519","signed_at":"2026-07-05T09:10:49.450809Z","signature_b64":"2DT620+8Mcg+5eDfm7iZKCq/hMdYcOthcNJB0jOYuj0O5zlyWm7ZjEf+wCqEcpeHy5xEywob5pXaofP4aOjdCg==","signed_message":"canonical_sha256_bytes","builder_version":"pith-number-builder-2026-05-17-v1","receipt_version":"0.3","canonical_sha256":"8f101c6f8c905811d418f907cbb223b26797f66f2e83a9fe09d57eb08a70db80","last_reissued_at":"2026-07-05T09:10:49.450236Z","signature_status":"signed_v1","first_computed_at":"2026-07-05T09:10:49.450236Z","public_key_fingerprint":"8d4b5ee74e4693bcd1df2446408b0d54"},"graph_snapshot":{"paper":{"title":"Scaling Deep Learning Computation over the Inter-Core Connected Intelligence Processor with T10","license":"http://creativecommons.org/licenses/by-nc-sa/4.0/","headline":"","cross_cats":["cs.LG"],"primary_cat":"cs.DC","authors_text":"Jian Huang, Jilong Xue, Lingxiao Ma, Yiqi Liu, Yu Cheng, Yuqi Xue, Ziming Miao","submitted_at":"2024-08-09T01:28:09Z","abstract_excerpt":"As AI chips incorporate numerous parallelized cores to scale deep learning (DL) computing, inter-core communication is enabled recently by employing high-bandwidth and low-latency interconnect links on the chip (e.g., Graphcore IPU). It allows each core to directly access the fast scratchpad memory in other cores, which enables new parallel computing paradigms. However, without proper support for the scalable inter-core connections in current DL compilers, it is hard for developers to exploit the benefits of this new architecture.\n  We present T10, the first DL compiler to exploit the inter-co"},"claims":{"count":0,"items":[],"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"source":{"id":"2408.04808","kind":"arxiv","version":2},"verdict":{"id":null,"model_set":{},"created_at":null,"strongest_claim":"","one_line_summary":"","pipeline_version":null,"weakest_assumption":"","pith_extraction_headline":""},"integrity":{"clean":true,"summary":{"advisory":0,"critical":0,"by_detector":{},"informational":0},"endpoint":"/pith/2408.04808/integrity.json","findings":[],"available":true,"detectors_run":[],"snapshot_sha256":"c28c3603d3b5d939e8dc4c7e95fa8dfce3d595e45f758748cecf8e644a296938"},"references":{"count":0,"sample":[],"resolved_work":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57","internal_anchors":0},"formal_canon":{"evidence_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"author_claims":{"count":0,"strong_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"builder_version":"pith-number-builder-2026-05-17-v1"},"aliases":[{"alias_kind":"arxiv","alias_value":"2408.04808","created_at":"2026-07-05T09:10:49.450289+00:00"},{"alias_kind":"arxiv_version","alias_value":"2408.04808v2","created_at":"2026-07-05T09:10:49.450289+00:00"},{"alias_kind":"doi","alias_value":"10.48550/arxiv.2408.04808","created_at":"2026-07-05T09:10:49.450289+00:00"},{"alias_kind":"pith_short_12","alias_value":"R4IBY34MSBMB","created_at":"2026-07-05T09:10:49.450289+00:00"},{"alias_kind":"pith_short_16","alias_value":"R4IBY34MSBMBDVAY","created_at":"2026-07-05T09:10:49.450289+00:00"},{"alias_kind":"pith_short_8","alias_value":"R4IBY34M","created_at":"2026-07-05T09:10:49.450289+00:00"}],"events":[],"event_summary":{},"paper_claims":[],"inbound_citations":{"count":1,"internal_anchor_count":1,"sample":[{"citing_arxiv_id":"2506.11446","citing_title":"Topology-Aware Virtualization over Inter-Core Connected Neural Processing Units","ref_index":49,"is_internal_anchor":true}]},"formal_canon":{"evidence_count":0,"sample":[],"anchors":[]},"links":{"html":"https://pith.science/pith/R4IBY34MSBMBDVAY7ED4XMRDWJ","json":"https://pith.science/pith/R4IBY34MSBMBDVAY7ED4XMRDWJ.json","graph_json":"https://pith.science/api/pith-number/R4IBY34MSBMBDVAY7ED4XMRDWJ/graph.json","events_json":"https://pith.science/api/pith-number/R4IBY34MSBMBDVAY7ED4XMRDWJ/events.json","paper":"https://pith.science/paper/R4IBY34M"},"agent_actions":{"view_html":"https://pith.science/pith/R4IBY34MSBMBDVAY7ED4XMRDWJ","download_json":"https://pith.science/pith/R4IBY34MSBMBDVAY7ED4XMRDWJ.json","view_paper":"https://pith.science/paper/R4IBY34M","resolve_alias":"https://pith.science/api/pith-number/resolve?arxiv=2408.04808&json=true","fetch_graph":"https://pith.science/api/pith-number/R4IBY34MSBMBDVAY7ED4XMRDWJ/graph.json","fetch_events":"https://pith.science/api/pith-number/R4IBY34MSBMBDVAY7ED4XMRDWJ/events.json","actions":{"anchor_timestamp":"https://pith.science/pith/R4IBY34MSBMBDVAY7ED4XMRDWJ/action/timestamp_anchor","attest_storage":"https://pith.science/pith/R4IBY34MSBMBDVAY7ED4XMRDWJ/action/storage_attestation","attest_author":"https://pith.science/pith/R4IBY34MSBMBDVAY7ED4XMRDWJ/action/author_attestation","sign_citation":"https://pith.science/pith/R4IBY34MSBMBDVAY7ED4XMRDWJ/action/citation_signature","submit_replication":"https://pith.science/pith/R4IBY34MSBMBDVAY7ED4XMRDWJ/action/replication_record"}},"created_at":"2026-07-05T09:10:49.450289+00:00","updated_at":"2026-07-05T09:10:49.450289+00:00"}