{"record_type":"pith_number_record","schema_url":"https://pith.science/schemas/pith-number/v1.json","pith_number":"pith:2025:R77MFT34I2MAJS3GWIHMPOMISB","short_pith_number":"pith:R77MFT34","schema_version":"1.0","canonical_sha256":"8ffec2cf7c469804cb66b20ec7b988905ee8cfd1744465fc1a2f853839eaab11","source":{"kind":"arxiv","id":"2507.10338","version":1},"attestation_state":"computed","paper":{"title":"AssertCoder: LLM-Based Assertion Generation via Multimodal Specification Extraction","license":"http://arxiv.org/licenses/nonexclusive-distrib/1.0/","headline":"","cross_cats":["cs.AR","cs.LO"],"primary_cat":"cs.SE","authors_text":"Enyuan Tian, Qiusong Yang, Yiwei Ci, Yufeng Li, Zhichao Lyu","submitted_at":"2025-07-14T14:43:14Z","abstract_excerpt":"Assertion-Based Verification (ABV) is critical for ensuring functional correctness in modern hardware systems. However, manually writing high-quality SVAs remains labor-intensive and error-prone. To bridge this gap, we propose AssertCoder, a novel unified framework that automatically generates high-quality SVAs directly from multimodal hardware design specifications. AssertCoder employs a modality-sensitive preprocessing to parse heterogeneous specification formats (text, tables, diagrams, and formulas), followed by a set of dedicated semantic analyzers that extract structured representations "},"verification_status":{"content_addressed":true,"pith_receipt":true,"author_attested":false,"weak_author_claims":0,"strong_author_claims":0,"externally_anchored":false,"storage_verified":false,"citation_signatures":0,"replication_records":0,"graph_snapshot":true,"references_resolved":false,"formal_links_present":false},"canonical_record":{"source":{"id":"2507.10338","kind":"arxiv","version":1},"metadata":{"license":"http://arxiv.org/licenses/nonexclusive-distrib/1.0/","primary_cat":"cs.SE","submitted_at":"2025-07-14T14:43:14Z","cross_cats_sorted":["cs.AR","cs.LO"],"title_canon_sha256":"1db189d9b6557c87410085e30cb472978198807e459c1c545da1bb0a157eb490","abstract_canon_sha256":"0abb3ce1f514438c32fdaa95ea21a7d866ee413f8bcc375c9526577e2e9b6d27"},"schema_version":"1.0"},"receipt":{"kind":"pith_receipt","key_id":"pith-v1-2026-05","algorithm":"ed25519","signed_at":"2026-07-05T11:36:49.817474Z","signature_b64":"/P2tXV30zi1aUrXWyys39VM01y9Dg/olD9dFiKFqB91M6YjACl3Y1rQaca8q61owl1j/FrT4ghOrwv1hCdpGCw==","signed_message":"canonical_sha256_bytes","builder_version":"pith-number-builder-2026-05-17-v1","receipt_version":"0.3","canonical_sha256":"8ffec2cf7c469804cb66b20ec7b988905ee8cfd1744465fc1a2f853839eaab11","last_reissued_at":"2026-07-05T11:36:49.816933Z","signature_status":"signed_v1","first_computed_at":"2026-07-05T11:36:49.816933Z","public_key_fingerprint":"8d4b5ee74e4693bcd1df2446408b0d54"},"graph_snapshot":{"paper":{"title":"AssertCoder: LLM-Based Assertion Generation via Multimodal Specification Extraction","license":"http://arxiv.org/licenses/nonexclusive-distrib/1.0/","headline":"","cross_cats":["cs.AR","cs.LO"],"primary_cat":"cs.SE","authors_text":"Enyuan Tian, Qiusong Yang, Yiwei Ci, Yufeng Li, Zhichao Lyu","submitted_at":"2025-07-14T14:43:14Z","abstract_excerpt":"Assertion-Based Verification (ABV) is critical for ensuring functional correctness in modern hardware systems. However, manually writing high-quality SVAs remains labor-intensive and error-prone. To bridge this gap, we propose AssertCoder, a novel unified framework that automatically generates high-quality SVAs directly from multimodal hardware design specifications. AssertCoder employs a modality-sensitive preprocessing to parse heterogeneous specification formats (text, tables, diagrams, and formulas), followed by a set of dedicated semantic analyzers that extract structured representations "},"claims":{"count":0,"items":[],"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"source":{"id":"2507.10338","kind":"arxiv","version":1},"verdict":{"id":null,"model_set":{},"created_at":null,"strongest_claim":"","one_line_summary":"","pipeline_version":null,"weakest_assumption":"","pith_extraction_headline":""},"integrity":{"clean":true,"summary":{"advisory":0,"critical":0,"by_detector":{},"informational":0},"endpoint":"/pith/2507.10338/integrity.json","findings":[],"available":true,"detectors_run":[],"snapshot_sha256":"c28c3603d3b5d939e8dc4c7e95fa8dfce3d595e45f758748cecf8e644a296938"},"references":{"count":0,"sample":[],"resolved_work":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57","internal_anchors":0},"formal_canon":{"evidence_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"author_claims":{"count":0,"strong_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"builder_version":"pith-number-builder-2026-05-17-v1"},"aliases":[{"alias_kind":"arxiv","alias_value":"2507.10338","created_at":"2026-07-05T11:36:49.816992+00:00"},{"alias_kind":"arxiv_version","alias_value":"2507.10338v1","created_at":"2026-07-05T11:36:49.816992+00:00"},{"alias_kind":"doi","alias_value":"10.48550/arxiv.2507.10338","created_at":"2026-07-05T11:36:49.816992+00:00"},{"alias_kind":"pith_short_12","alias_value":"R77MFT34I2MA","created_at":"2026-07-05T11:36:49.816992+00:00"},{"alias_kind":"pith_short_16","alias_value":"R77MFT34I2MAJS3G","created_at":"2026-07-05T11:36:49.816992+00:00"},{"alias_kind":"pith_short_8","alias_value":"R77MFT34","created_at":"2026-07-05T11:36:49.816992+00:00"}],"events":[],"event_summary":{},"paper_claims":[],"inbound_citations":{"count":4,"internal_anchor_count":1,"sample":[{"citing_arxiv_id":"2607.07444","citing_title":"LLM Assisted Verification Assertion Generation: Challenges and Future Directions","ref_index":13,"is_internal_anchor":true},{"citing_arxiv_id":"2606.25296","citing_title":"SafeGen: LLM-Driven Assertion Generation and Fault Criticality Evaluation for Functional Safety","ref_index":42,"is_internal_anchor":false},{"citing_arxiv_id":"2605.27472","citing_title":"AssertLLM2: A Comprehensive LLM Benchmark for Assertion Generation from Design Specifications","ref_index":6,"is_internal_anchor":false},{"citing_arxiv_id":"2605.00058","citing_title":"Autoformalizing Memory Specifications with Agents","ref_index":41,"is_internal_anchor":false}]},"formal_canon":{"evidence_count":0,"sample":[],"anchors":[]},"links":{"html":"https://pith.science/pith/R77MFT34I2MAJS3GWIHMPOMISB","json":"https://pith.science/pith/R77MFT34I2MAJS3GWIHMPOMISB.json","graph_json":"https://pith.science/api/pith-number/R77MFT34I2MAJS3GWIHMPOMISB/graph.json","events_json":"https://pith.science/api/pith-number/R77MFT34I2MAJS3GWIHMPOMISB/events.json","paper":"https://pith.science/paper/R77MFT34"},"agent_actions":{"view_html":"https://pith.science/pith/R77MFT34I2MAJS3GWIHMPOMISB","download_json":"https://pith.science/pith/R77MFT34I2MAJS3GWIHMPOMISB.json","view_paper":"https://pith.science/paper/R77MFT34","resolve_alias":"https://pith.science/api/pith-number/resolve?arxiv=2507.10338&json=true","fetch_graph":"https://pith.science/api/pith-number/R77MFT34I2MAJS3GWIHMPOMISB/graph.json","fetch_events":"https://pith.science/api/pith-number/R77MFT34I2MAJS3GWIHMPOMISB/events.json","actions":{"anchor_timestamp":"https://pith.science/pith/R77MFT34I2MAJS3GWIHMPOMISB/action/timestamp_anchor","attest_storage":"https://pith.science/pith/R77MFT34I2MAJS3GWIHMPOMISB/action/storage_attestation","attest_author":"https://pith.science/pith/R77MFT34I2MAJS3GWIHMPOMISB/action/author_attestation","sign_citation":"https://pith.science/pith/R77MFT34I2MAJS3GWIHMPOMISB/action/citation_signature","submit_replication":"https://pith.science/pith/R77MFT34I2MAJS3GWIHMPOMISB/action/replication_record"}},"created_at":"2026-07-05T11:36:49.816992+00:00","updated_at":"2026-07-05T11:36:49.816992+00:00"}