{"record_type":"pith_number_record","schema_url":"https://pith.science/schemas/pith-number/v1.json","pith_number":"pith:2024:YCCMXIU44PL2V5NLV4KR4EK3RV","short_pith_number":"pith:YCCMXIU4","schema_version":"1.0","canonical_sha256":"c084cba29ce3d7aaf5abaf151e115b8d4c7b99bdb9ddfdb1fa3a09cd61f9b6eb","source":{"kind":"arxiv","id":"2411.09317","version":1},"attestation_state":"computed","paper":{"title":"Pie: Pooling CPU Memory for LLM Inference","license":"http://arxiv.org/licenses/nonexclusive-distrib/1.0/","headline":"","cross_cats":["cs.DC"],"primary_cat":"cs.LG","authors_text":"Ion Stoica, Shu Liu, Xiangxi Mo, Yi Xu, Ziming Mao","submitted_at":"2024-11-14T09:50:41Z","abstract_excerpt":"The rapid growth of LLMs has revolutionized natural language processing and AI analysis, but their increasing size and memory demands present significant challenges. A common solution is to spill over to CPU memory; however, traditional GPU-CPU memory swapping often results in higher latency and lower throughput.\n  This paper introduces Pie, an LLM inference framework that addresses these challenges with performance-transparent swapping and adaptive expansion. By leveraging predictable memory access patterns and the high bandwidth of modern hardware like the NVIDIA GH200 Grace Hopper Superchip"},"verification_status":{"content_addressed":true,"pith_receipt":true,"author_attested":false,"weak_author_claims":0,"strong_author_claims":0,"externally_anchored":false,"storage_verified":false,"citation_signatures":0,"replication_records":0,"graph_snapshot":true,"references_resolved":false,"formal_links_present":false},"canonical_record":{"source":{"id":"2411.09317","kind":"arxiv","version":1},"metadata":{"license":"http://arxiv.org/licenses/nonexclusive-distrib/1.0/","primary_cat":"cs.LG","submitted_at":"2024-11-14T09:50:41Z","cross_cats_sorted":["cs.DC"],"title_canon_sha256":"7bebada8f898cfaf9dc5fba20244ecd3a7da3438d54949779920f755e0dd2736","abstract_canon_sha256":"2fb0401c81fa9b048ab2eb02e75a4aa47a803534ce604df1d177dc5d86b44a43"},"schema_version":"1.0"},"receipt":{"kind":"pith_receipt","key_id":"pith-v1-2026-05","algorithm":"ed25519","signed_at":"2026-07-05T09:35:25.032839Z","signature_b64":"Kj42O0vADs0ZXMZ4DxJSFycB0E8IjQIEa0r70cK73gRg4WAGPlBpvumimJazJzWZ6PLFDadjUYfg1aHQXqjcDQ==","signed_message":"canonical_sha256_bytes","builder_version":"pith-number-builder-2026-05-17-v1","receipt_version":"0.3","canonical_sha256":"c084cba29ce3d7aaf5abaf151e115b8d4c7b99bdb9ddfdb1fa3a09cd61f9b6eb","last_reissued_at":"2026-07-05T09:35:25.032328Z","signature_status":"signed_v1","first_computed_at":"2026-07-05T09:35:25.032328Z","public_key_fingerprint":"8d4b5ee74e4693bcd1df2446408b0d54"},"graph_snapshot":{"paper":{"title":"Pie: Pooling CPU Memory for LLM Inference","license":"http://arxiv.org/licenses/nonexclusive-distrib/1.0/","headline":"","cross_cats":["cs.DC"],"primary_cat":"cs.LG","authors_text":"Ion Stoica, Shu Liu, Xiangxi Mo, Yi Xu, Ziming Mao","submitted_at":"2024-11-14T09:50:41Z","abstract_excerpt":"The rapid growth of LLMs has revolutionized natural language processing and AI analysis, but their increasing size and memory demands present significant challenges. A common solution is to spill over to CPU memory; however, traditional GPU-CPU memory swapping often results in higher latency and lower throughput.\n  This paper introduces Pie, an LLM inference framework that addresses these challenges with performance-transparent swapping and adaptive expansion. By leveraging predictable memory access patterns and the high bandwidth of modern hardware like the NVIDIA GH200 Grace Hopper Superchip"},"claims":{"count":0,"items":[],"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"source":{"id":"2411.09317","kind":"arxiv","version":1},"verdict":{"id":null,"model_set":{},"created_at":null,"strongest_claim":"","one_line_summary":"","pipeline_version":null,"weakest_assumption":"","pith_extraction_headline":""},"integrity":{"clean":true,"summary":{"advisory":0,"critical":0,"by_detector":{},"informational":0},"endpoint":"/pith/2411.09317/integrity.json","findings":[],"available":true,"detectors_run":[],"snapshot_sha256":"c28c3603d3b5d939e8dc4c7e95fa8dfce3d595e45f758748cecf8e644a296938"},"references":{"count":0,"sample":[],"resolved_work":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57","internal_anchors":0},"formal_canon":{"evidence_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"author_claims":{"count":0,"strong_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"builder_version":"pith-number-builder-2026-05-17-v1"},"aliases":[{"alias_kind":"arxiv","alias_value":"2411.09317","created_at":"2026-07-05T09:35:25.032391+00:00"},{"alias_kind":"arxiv_version","alias_value":"2411.09317v1","created_at":"2026-07-05T09:35:25.032391+00:00"},{"alias_kind":"doi","alias_value":"10.48550/arxiv.2411.09317","created_at":"2026-07-05T09:35:25.032391+00:00"},{"alias_kind":"pith_short_12","alias_value":"YCCMXIU44PL2","created_at":"2026-07-05T09:35:25.032391+00:00"},{"alias_kind":"pith_short_16","alias_value":"YCCMXIU44PL2V5NL","created_at":"2026-07-05T09:35:25.032391+00:00"},{"alias_kind":"pith_short_8","alias_value":"YCCMXIU4","created_at":"2026-07-05T09:35:25.032391+00:00"}],"events":[],"event_summary":{},"paper_claims":[],"inbound_citations":{"count":5,"internal_anchor_count":0,"sample":[{"citing_arxiv_id":"2606.00866","citing_title":"Idleness is Relative: Exploiting Tool-Call Idle Windows for Offloading in Agentic Systems with MORI","ref_index":64,"is_internal_anchor":false},{"citing_arxiv_id":"2605.28095","citing_title":"SiDP: Memory-Efficient Data Parallelism for Offline LLM Inference","ref_index":31,"is_internal_anchor":false},{"citing_arxiv_id":"2601.20309","citing_title":"SuperInfer: SLO-Aware Rotary Scheduling and Memory Management for LLM Inference on Superchips","ref_index":21,"is_internal_anchor":false},{"citing_arxiv_id":"2605.19481","citing_title":"C2CServe: Leveraging NVLink-C2C for Elastic Serverless LLM Serving on MIG","ref_index":43,"is_internal_anchor":false},{"citing_arxiv_id":"2604.26074","citing_title":"DAK: Direct-Access-Enabled GPU Memory Offloading with Optimal Efficiency for LLM Inference","ref_index":37,"is_internal_anchor":false}]},"formal_canon":{"evidence_count":0,"sample":[],"anchors":[]},"links":{"html":"https://pith.science/pith/YCCMXIU44PL2V5NLV4KR4EK3RV","json":"https://pith.science/pith/YCCMXIU44PL2V5NLV4KR4EK3RV.json","graph_json":"https://pith.science/api/pith-number/YCCMXIU44PL2V5NLV4KR4EK3RV/graph.json","events_json":"https://pith.science/api/pith-number/YCCMXIU44PL2V5NLV4KR4EK3RV/events.json","paper":"https://pith.science/paper/YCCMXIU4"},"agent_actions":{"view_html":"https://pith.science/pith/YCCMXIU44PL2V5NLV4KR4EK3RV","download_json":"https://pith.science/pith/YCCMXIU44PL2V5NLV4KR4EK3RV.json","view_paper":"https://pith.science/paper/YCCMXIU4","resolve_alias":"https://pith.science/api/pith-number/resolve?arxiv=2411.09317&json=true","fetch_graph":"https://pith.science/api/pith-number/YCCMXIU44PL2V5NLV4KR4EK3RV/graph.json","fetch_events":"https://pith.science/api/pith-number/YCCMXIU44PL2V5NLV4KR4EK3RV/events.json","actions":{"anchor_timestamp":"https://pith.science/pith/YCCMXIU44PL2V5NLV4KR4EK3RV/action/timestamp_anchor","attest_storage":"https://pith.science/pith/YCCMXIU44PL2V5NLV4KR4EK3RV/action/storage_attestation","attest_author":"https://pith.science/pith/YCCMXIU44PL2V5NLV4KR4EK3RV/action/author_attestation","sign_citation":"https://pith.science/pith/YCCMXIU44PL2V5NLV4KR4EK3RV/action/citation_signature","submit_replication":"https://pith.science/pith/YCCMXIU44PL2V5NLV4KR4EK3RV/action/replication_record"}},"created_at":"2026-07-05T09:35:25.032391+00:00","updated_at":"2026-07-05T09:35:25.032391+00:00"}