{"record_type":"pith_number_record","schema_url":"https://pith.science/schemas/pith-number/v1.json","pith_number":"pith:2023:YNPBOZ72K5WJ2PFSNRXJ5QEJWN","short_pith_number":"pith:YNPBOZ72","schema_version":"1.0","canonical_sha256":"c35e1767fa576c9d3cb26c6e9ec089b37c0838b10387d9ef00ed668c87ac01d3","source":{"kind":"arxiv","id":"2309.09437","version":2},"attestation_state":"computed","paper":{"title":"Using LLMs to Facilitate Formal Verification of RTL","license":"http://creativecommons.org/licenses/by/4.0/","headline":"","cross_cats":["cs.SE"],"primary_cat":"cs.AR","authors_text":"David Wentzlaff, Marcelo Orenes-Vera, Margaret Martonosi","submitted_at":"2023-09-18T02:37:43Z","abstract_excerpt":"Formal property verification (FPV) has existed for decades and has been shown to be effective at finding intricate RTL bugs. However, formal properties, such as those written as SystemVerilog Assertions (SVA), are time-consuming and error-prone to write, even for experienced users. Prior work has attempted to lighten this burden by raising the abstraction level so that SVA is generated from high-level specifications. However, this does not eliminate the manual effort of reasoning and writing about the detailed hardware behavior. Motivated by the increased need for FPV in the era of heterogeneo"},"verification_status":{"content_addressed":true,"pith_receipt":true,"author_attested":false,"weak_author_claims":0,"strong_author_claims":0,"externally_anchored":false,"storage_verified":false,"citation_signatures":0,"replication_records":0,"graph_snapshot":true,"references_resolved":false,"formal_links_present":false},"canonical_record":{"source":{"id":"2309.09437","kind":"arxiv","version":2},"metadata":{"license":"http://creativecommons.org/licenses/by/4.0/","primary_cat":"cs.AR","submitted_at":"2023-09-18T02:37:43Z","cross_cats_sorted":["cs.SE"],"title_canon_sha256":"d6b770a1f8fd33336262d97776ec7b7ffb2c4df0b6dbaf13cffddf79e0979ca8","abstract_canon_sha256":"fcee956feb59bfd161fc054824288d1a24897f6b3ce54a8ca0364d3da9b41138"},"schema_version":"1.0"},"receipt":{"kind":"pith_receipt","key_id":"pith-v1-2026-05","algorithm":"ed25519","signed_at":"2026-07-05T09:25:33.352917Z","signature_b64":"/Cd/sG7K7n4NHL1mbNGm81Rl3sAlp/RL70SOMdTa68Au5+i2dgP6KbQzDaxrcUoJ+eIz4Acf3HCyRwgEm0x6BA==","signed_message":"canonical_sha256_bytes","builder_version":"pith-number-builder-2026-05-17-v1","receipt_version":"0.3","canonical_sha256":"c35e1767fa576c9d3cb26c6e9ec089b37c0838b10387d9ef00ed668c87ac01d3","last_reissued_at":"2026-07-05T09:25:33.352532Z","signature_status":"signed_v1","first_computed_at":"2026-07-05T09:25:33.352532Z","public_key_fingerprint":"8d4b5ee74e4693bcd1df2446408b0d54"},"graph_snapshot":{"paper":{"title":"Using LLMs to Facilitate Formal Verification of RTL","license":"http://creativecommons.org/licenses/by/4.0/","headline":"","cross_cats":["cs.SE"],"primary_cat":"cs.AR","authors_text":"David Wentzlaff, Marcelo Orenes-Vera, Margaret Martonosi","submitted_at":"2023-09-18T02:37:43Z","abstract_excerpt":"Formal property verification (FPV) has existed for decades and has been shown to be effective at finding intricate RTL bugs. However, formal properties, such as those written as SystemVerilog Assertions (SVA), are time-consuming and error-prone to write, even for experienced users. Prior work has attempted to lighten this burden by raising the abstraction level so that SVA is generated from high-level specifications. However, this does not eliminate the manual effort of reasoning and writing about the detailed hardware behavior. Motivated by the increased need for FPV in the era of heterogeneo"},"claims":{"count":0,"items":[],"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"source":{"id":"2309.09437","kind":"arxiv","version":2},"verdict":{"id":null,"model_set":{},"created_at":null,"strongest_claim":"","one_line_summary":"","pipeline_version":null,"weakest_assumption":"","pith_extraction_headline":""},"integrity":{"clean":true,"summary":{"advisory":0,"critical":0,"by_detector":{},"informational":0},"endpoint":"/pith/2309.09437/integrity.json","findings":[],"available":true,"detectors_run":[],"snapshot_sha256":"c28c3603d3b5d939e8dc4c7e95fa8dfce3d595e45f758748cecf8e644a296938"},"references":{"count":0,"sample":[],"resolved_work":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57","internal_anchors":0},"formal_canon":{"evidence_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"author_claims":{"count":0,"strong_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"builder_version":"pith-number-builder-2026-05-17-v1"},"aliases":[{"alias_kind":"arxiv","alias_value":"2309.09437","created_at":"2026-07-05T09:25:33.352587+00:00"},{"alias_kind":"arxiv_version","alias_value":"2309.09437v2","created_at":"2026-07-05T09:25:33.352587+00:00"},{"alias_kind":"doi","alias_value":"10.48550/arxiv.2309.09437","created_at":"2026-07-05T09:25:33.352587+00:00"},{"alias_kind":"pith_short_12","alias_value":"YNPBOZ72K5WJ","created_at":"2026-07-05T09:25:33.352587+00:00"},{"alias_kind":"pith_short_16","alias_value":"YNPBOZ72K5WJ2PFS","created_at":"2026-07-05T09:25:33.352587+00:00"},{"alias_kind":"pith_short_8","alias_value":"YNPBOZ72","created_at":"2026-07-05T09:25:33.352587+00:00"}],"events":[],"event_summary":{},"paper_claims":[],"inbound_citations":{"count":7,"internal_anchor_count":1,"sample":[{"citing_arxiv_id":"2607.07444","citing_title":"LLM Assisted Verification Assertion Generation: Challenges and Future Directions","ref_index":6,"is_internal_anchor":true},{"citing_arxiv_id":"2511.02521","citing_title":"Large Lemma Miners: Can LLMs do Induction Proofs for Hardware?","ref_index":27,"is_internal_anchor":false},{"citing_arxiv_id":"2511.20284","citing_title":"Can LLMs Make (Personalized) Access Control Decisions?","ref_index":3,"is_internal_anchor":false},{"citing_arxiv_id":"2604.02811","citing_title":"ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs","ref_index":23,"is_internal_anchor":false},{"citing_arxiv_id":"2604.23100","citing_title":"From Language to Logic: Bridging LLMs & Formal Representations for RTL Assertion Generation","ref_index":11,"is_internal_anchor":false},{"citing_arxiv_id":"2604.11044","citing_title":"Automated SVA Generation with LLMs","ref_index":28,"is_internal_anchor":false},{"citing_arxiv_id":"2604.06607","citing_title":"CoverAssert: Iterative LLM Assertion Generation Driven by Functional Coverage via Syntax-Semantic Representations","ref_index":11,"is_internal_anchor":false}]},"formal_canon":{"evidence_count":0,"sample":[],"anchors":[]},"links":{"html":"https://pith.science/pith/YNPBOZ72K5WJ2PFSNRXJ5QEJWN","json":"https://pith.science/pith/YNPBOZ72K5WJ2PFSNRXJ5QEJWN.json","graph_json":"https://pith.science/api/pith-number/YNPBOZ72K5WJ2PFSNRXJ5QEJWN/graph.json","events_json":"https://pith.science/api/pith-number/YNPBOZ72K5WJ2PFSNRXJ5QEJWN/events.json","paper":"https://pith.science/paper/YNPBOZ72"},"agent_actions":{"view_html":"https://pith.science/pith/YNPBOZ72K5WJ2PFSNRXJ5QEJWN","download_json":"https://pith.science/pith/YNPBOZ72K5WJ2PFSNRXJ5QEJWN.json","view_paper":"https://pith.science/paper/YNPBOZ72","resolve_alias":"https://pith.science/api/pith-number/resolve?arxiv=2309.09437&json=true","fetch_graph":"https://pith.science/api/pith-number/YNPBOZ72K5WJ2PFSNRXJ5QEJWN/graph.json","fetch_events":"https://pith.science/api/pith-number/YNPBOZ72K5WJ2PFSNRXJ5QEJWN/events.json","actions":{"anchor_timestamp":"https://pith.science/pith/YNPBOZ72K5WJ2PFSNRXJ5QEJWN/action/timestamp_anchor","attest_storage":"https://pith.science/pith/YNPBOZ72K5WJ2PFSNRXJ5QEJWN/action/storage_attestation","attest_author":"https://pith.science/pith/YNPBOZ72K5WJ2PFSNRXJ5QEJWN/action/author_attestation","sign_citation":"https://pith.science/pith/YNPBOZ72K5WJ2PFSNRXJ5QEJWN/action/citation_signature","submit_replication":"https://pith.science/pith/YNPBOZ72K5WJ2PFSNRXJ5QEJWN/action/replication_record"}},"created_at":"2026-07-05T09:25:33.352587+00:00","updated_at":"2026-07-05T09:25:33.352587+00:00"}