{"record_type":"pith_number_record","schema_url":"https://pith.science/schemas/pith-number/v1.json","pith_number":"pith:2020:ZVFDV23HD25KKNJQBMZBNTD5LN","short_pith_number":"pith:ZVFDV23H","schema_version":"1.0","canonical_sha256":"cd4a3aeb671ebaa535300b3216cc7d5b6dd74d8edad478ad4c3fca421afaea88","source":{"kind":"arxiv","id":"2003.11455","version":1},"attestation_state":"computed","paper":{"title":"Verification and Design Methods for the BrainScaleS Neuromorphic Hardware System","license":"http://arxiv.org/licenses/nonexclusive-distrib/1.0/","headline":"","cross_cats":["cs.NE"],"primary_cat":"cs.AR","authors_text":"Andreas Gr\\\"ubl, Benjamin Cramer, Johannes Schemmel, Sebastian Billaudelle, Vitali Karasenko","submitted_at":"2020-03-25T15:48:54Z","abstract_excerpt":"This paper presents verification and implementation methods that have been developed for the design of the BrainScaleS-2 65nm ASICs. The 2nd generation BrainScaleS chips are mixed-signal devices with tight coupling between full-custom analog neuromorphic circuits and two general purpose microprocessors (PPU) with SIMD extension for on-chip learning and plasticity. Simulation methods for automated analysis and pre-tapeout calibration of the highly parameterizable analog neuron and synapse circuits and for hardware-software co-development of the digital logic and software stack are presented. Ac"},"verification_status":{"content_addressed":true,"pith_receipt":true,"author_attested":false,"weak_author_claims":0,"strong_author_claims":0,"externally_anchored":false,"storage_verified":false,"citation_signatures":0,"replication_records":0,"graph_snapshot":true,"references_resolved":false,"formal_links_present":false},"canonical_record":{"source":{"id":"2003.11455","kind":"arxiv","version":1},"metadata":{"license":"http://arxiv.org/licenses/nonexclusive-distrib/1.0/","primary_cat":"cs.AR","submitted_at":"2020-03-25T15:48:54Z","cross_cats_sorted":["cs.NE"],"title_canon_sha256":"b29b8727f8966f6317be9974ab4bbaf97842748408469bd2629a003d09916d7f","abstract_canon_sha256":"cf40d53410e0ae3320a1c60451bcec96320115675b954af5882401930dd06a2a"},"schema_version":"1.0"},"receipt":{"kind":"pith_receipt","key_id":"pith-v1-2026-05","algorithm":"ed25519","signed_at":"2026-07-05T00:50:34.470512Z","signature_b64":"eT8aFPpsjHWn8m8eN5CFjSCJjoDPChd80GNVknGXoVfmxIQ4GYAskgr1TICSfiQ2oG95Hnnz8APE/hEsEPgXAA==","signed_message":"canonical_sha256_bytes","builder_version":"pith-number-builder-2026-05-17-v1","receipt_version":"0.3","canonical_sha256":"cd4a3aeb671ebaa535300b3216cc7d5b6dd74d8edad478ad4c3fca421afaea88","last_reissued_at":"2026-07-05T00:50:34.470083Z","signature_status":"signed_v1","first_computed_at":"2026-07-05T00:50:34.470083Z","public_key_fingerprint":"8d4b5ee74e4693bcd1df2446408b0d54"},"graph_snapshot":{"paper":{"title":"Verification and Design Methods for the BrainScaleS Neuromorphic Hardware System","license":"http://arxiv.org/licenses/nonexclusive-distrib/1.0/","headline":"","cross_cats":["cs.NE"],"primary_cat":"cs.AR","authors_text":"Andreas Gr\\\"ubl, Benjamin Cramer, Johannes Schemmel, Sebastian Billaudelle, Vitali Karasenko","submitted_at":"2020-03-25T15:48:54Z","abstract_excerpt":"This paper presents verification and implementation methods that have been developed for the design of the BrainScaleS-2 65nm ASICs. The 2nd generation BrainScaleS chips are mixed-signal devices with tight coupling between full-custom analog neuromorphic circuits and two general purpose microprocessors (PPU) with SIMD extension for on-chip learning and plasticity. Simulation methods for automated analysis and pre-tapeout calibration of the highly parameterizable analog neuron and synapse circuits and for hardware-software co-development of the digital logic and software stack are presented. Ac"},"claims":{"count":0,"items":[],"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"source":{"id":"2003.11455","kind":"arxiv","version":1},"verdict":{"id":null,"model_set":{},"created_at":null,"strongest_claim":"","one_line_summary":"","pipeline_version":null,"weakest_assumption":"","pith_extraction_headline":""},"integrity":{"clean":true,"summary":{"advisory":0,"critical":0,"by_detector":{},"informational":0},"endpoint":"/pith/2003.11455/integrity.json","findings":[],"available":true,"detectors_run":[],"snapshot_sha256":"c28c3603d3b5d939e8dc4c7e95fa8dfce3d595e45f758748cecf8e644a296938"},"references":{"count":0,"sample":[],"resolved_work":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57","internal_anchors":0},"formal_canon":{"evidence_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"author_claims":{"count":0,"strong_count":0,"snapshot_sha256":"258153158e38e3291e3d48162225fcdb2d5a3ed65a07baac614ab91432fd4f57"},"builder_version":"pith-number-builder-2026-05-17-v1"},"aliases":[{"alias_kind":"arxiv","alias_value":"2003.11455","created_at":"2026-07-05T00:50:34.470148+00:00"},{"alias_kind":"arxiv_version","alias_value":"2003.11455v1","created_at":"2026-07-05T00:50:34.470148+00:00"},{"alias_kind":"doi","alias_value":"10.48550/arxiv.2003.11455","created_at":"2026-07-05T00:50:34.470148+00:00"},{"alias_kind":"pith_short_12","alias_value":"ZVFDV23HD25K","created_at":"2026-07-05T00:50:34.470148+00:00"},{"alias_kind":"pith_short_16","alias_value":"ZVFDV23HD25KKNJQ","created_at":"2026-07-05T00:50:34.470148+00:00"},{"alias_kind":"pith_short_8","alias_value":"ZVFDV23H","created_at":"2026-07-05T00:50:34.470148+00:00"}],"events":[],"event_summary":{},"paper_claims":[],"inbound_citations":{"count":1,"internal_anchor_count":1,"sample":[{"citing_arxiv_id":"2412.20848","citing_title":"Analog Alchemy: Neural Computation with In-Memory Inference, Learning and Routing","ref_index":90,"is_internal_anchor":true}]},"formal_canon":{"evidence_count":0,"sample":[],"anchors":[]},"links":{"html":"https://pith.science/pith/ZVFDV23HD25KKNJQBMZBNTD5LN","json":"https://pith.science/pith/ZVFDV23HD25KKNJQBMZBNTD5LN.json","graph_json":"https://pith.science/api/pith-number/ZVFDV23HD25KKNJQBMZBNTD5LN/graph.json","events_json":"https://pith.science/api/pith-number/ZVFDV23HD25KKNJQBMZBNTD5LN/events.json","paper":"https://pith.science/paper/ZVFDV23H"},"agent_actions":{"view_html":"https://pith.science/pith/ZVFDV23HD25KKNJQBMZBNTD5LN","download_json":"https://pith.science/pith/ZVFDV23HD25KKNJQBMZBNTD5LN.json","view_paper":"https://pith.science/paper/ZVFDV23H","resolve_alias":"https://pith.science/api/pith-number/resolve?arxiv=2003.11455&json=true","fetch_graph":"https://pith.science/api/pith-number/ZVFDV23HD25KKNJQBMZBNTD5LN/graph.json","fetch_events":"https://pith.science/api/pith-number/ZVFDV23HD25KKNJQBMZBNTD5LN/events.json","actions":{"anchor_timestamp":"https://pith.science/pith/ZVFDV23HD25KKNJQBMZBNTD5LN/action/timestamp_anchor","attest_storage":"https://pith.science/pith/ZVFDV23HD25KKNJQBMZBNTD5LN/action/storage_attestation","attest_author":"https://pith.science/pith/ZVFDV23HD25KKNJQBMZBNTD5LN/action/author_attestation","sign_citation":"https://pith.science/pith/ZVFDV23HD25KKNJQBMZBNTD5LN/action/citation_signature","submit_replication":"https://pith.science/pith/ZVFDV23HD25KKNJQBMZBNTD5LN/action/replication_record"}},"created_at":"2026-07-05T00:50:34.470148+00:00","updated_at":"2026-07-05T00:50:34.470148+00:00"}