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Massoud Pedram

Identifiers

  • name variant Massoud Pedram 0.60 · backfill

Papers (39)

  1. COFT: Counterfactual-Conformal Decoding for Fair Chain-of-Thought Reasoning in Large Language Models cs.CL · 2026 · author #3
  2. TimingLLM: A Two-Stage Retrieval-Augmented Framework for Pre-Synthesis Timing Prediction from Verilog cs.AR · 2026 · author #4
  3. One Token Away from Collapse: The Fragility of Instruction-Tuned Helpfulness cs.CL · 2026 · author #4
  4. Sense Less, Infer More: Agentic Multimodal Transformers for Edge Medical Intelligence cs.ET · 2026 · author #8
  5. qPRO-AQFP: Post-Routing Optimization of AQFP Circuits with Delay Line Clocking cs.ET · 2026 · author #5
  6. Inductorless Fast Phase Logic: Enabling Two-Order-of-Magnitude Density Scaling for Superconductor VLSI cond-mat.supr-con · 2026 · author #3
  7. SkipKV: Selective Skipping of KV Generation and Storage for Efficient Inference with Large Reasoning Models cs.AI · 2025 · author #9
  8. Top-H Decoding: Adapting the Creativity and Coherence with Bounded Entropy in Text Generation cs.CL · 2025 · author #4
  9. Optimizing Routerless Network-on-Chip Designs: An Innovative Learning-Based Framework cs.AR · 2019 · author #3
  10. Energy-Aware Scheduling of Task Graphs with Imprecise Computations and End-to-End Deadlines cs.DC · 2019 · author #3
  11. VeriSFQ - A Semi-formal Verification Framework and Benchmark for Single Flux Quantum Technology cs.ET · 2019 · author #5
  12. BottleNet: A Deep Learning Architecture for Intelligent Mobile Cloud Computing Services cs.DC · 2019 · author #3
  13. Hybrid Cell Assignment and Sizing for Power, Area, Delay Product Optimization of SRAM Arrays cs.AR · 2019 · author #3
  14. Approximate Logic Synthesis: A Reinforcement Learning-Based Technology Mapping Approach cs.AR · 2019 · author #3
  15. Towards Collaborative Intelligence Friendly Architectures for Deep Learning cs.DC · 2019 · author #3
  16. SFQmap: A Technology Mapping Tool for Single Flux Quantum Logic Circuits cs.ET · 2019 · author #3
  17. Space Expansion of Feature Selection for Designing more Accurate Error Predictors cs.LG · 2018 · author #4
  18. PBMap: A Path Balancing Technology Mapping Algorithm for Single Flux Quantum Logic Circuits cs.ET · 2018 · author #2
  19. Modeling Processor Idle Times in MPSoC Platforms to Enable Integrated DPM, DVFS, and Task Scheduling Subject to a Hard Deadline cs.OS · 2018 · author #3
  20. Gradient Agreement as an Optimization Objective for Meta-Learning cs.LG · 2018 · author #3
  21. A Graph Partitioning Algorithm with Application in Synthesizing Single Flux Quantum Logic Circuits cs.ET · 2018 · author #2
  22. A Meta-Learning Approach for Custom Model Training cs.LG · 2018 · author #4
  23. SpRRAM: A Predefined Sparsity Based Memristive Neuromorphic Circuit for Low Power Application cs.ET · 2018 · author #5
  24. NullaNet: Training Deep Neural Networks for Reduced-Memory-Access Inference cs.LG · 2018 · author #3
  25. Deploying Customized Data Representation and Approximate Computing in Machine Learning Applications cs.LG · 2018 · author #2
  26. VIBNN: Hardware Acceleration of Bayesian Neural Networks cs.LG · 2018 · author #7
  27. A Hardware-Friendly Algorithm for Scalable Training and Deployment of Dimensionality Reduction Models on FPGA cs.LG · 2018 · author #3
  28. FFT-Based Deep Learning Deployment in Embedded Systems cs.LG · 2017 · author #7
  29. High-Performance FPGA Implementation of Equivariant Adaptive Separation via Independence Algorithm for Independent Component Analysis cs.LG · 2017 · author #3
  30. Squash 2: A Hierarchical Scalable Quantum Mapper Considering Ancilla Sharing quant-ph · 2015 · author #3
  31. Design of a Universal Logic Block for Fault-Tolerant Realization of any Logic Operation in Trapped-Ion Quantum Circuits quant-ph · 2015 · author #4
  32. LEQA: Latency Estimation for a Quantum Algorithm Mapped to a Quantum Circuit Fabric quant-ph · 2015 · author #2
  33. Squash: A Scalable Quantum Mapper Considering Ancilla Sharing cs.ET · 2014 · author #3
  34. Minimizing the Latency of Quantum Circuits during Mapping to the Ion-Trap Circuit Fabric cs.ET · 2014 · author #2
  35. Constant-Factor Optimization of Quantum Adders on 2D Quantum Architectures quant-ph · 2013 · author #3
  36. Linear-Depth Quantum Circuits for n-qubit Toffoli gates with no Ancilla quant-ph · 2013 · author #2
  37. Reversible Logic Synthesis by Quantum Rotation Gates cs.ET · 2013 · author #3
  38. HEBS: Histogram Equalization for Backlight Scaling cs.OH · 2007 · author #3
  39. Modeling and Propagation of Noisy Waveforms in Static Timing Analysis cs.OH · 2007 · author #2

Mentions

  • 2605.30641 #3 · arxiv_oai · confidence 0.70 Massoud Pedram
  • 1304.0432 #3 · backfill · confidence 0.70 Massoud Pedram
  • 1303.3557 #2 · backfill · confidence 0.70 Massoud Pedram
  • 1302.5382 #3 · backfill · confidence 0.70 Massoud Pedram
  • 0710.4710 #3 · backfill · confidence 0.70 Massoud Pedram
  • 0710.4642 #2 · backfill · confidence 0.70 Massoud Pedram

Frequent Coauthors