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Ulf Schlichtmann

Identifiers

  • name variant Ulf Schlichtmann 0.60 · backfill

Papers (20)

  1. KV Packet: Recomputation-Free Context-Independent KV Caching for LLMs cs.LG · 2026 · author #6
  2. Transport or Store? Synthesizing Flow-based Microfluidic Biochips using Distributed Channel Storage cs.ET · 2017 · author #6
  3. Testing Microfluidic Fully Programmable Valve Arrays (FPVAs) cs.ET · 2017 · author #6
  4. Design-Phase Buffer Allocation for Post-Silicon Clock Binning by Iterative Learning cs.AR · 2017 · author #5
  5. PieceTimer: A Holistic Timing Analysis Framework Considering Setup/Hold Time Interdependency Using A Piecewise Model cs.AR · 2017 · author #3
  6. EffiTest: Efficient Delay Test and Statistical Prediction for Configuring Post-silicon Tunable Buffers cs.AR · 2017 · author #3
  7. Novel CMOS RFIC Layout Generation with Concurrent Device Placement and Fixed-Length Microstrip Routing cs.ET · 2017 · author #7
  8. Sampling-based Buffer Insertion for Post-Silicon Yield Improvement under Process Variability cs.AR · 2017 · author #3
  9. Storage and Caching: Synthesis of Flow-based Microfluidic Biochips cs.ET · 2017 · author #4
  10. Statistical Timing Analysis and Criticality Computation for Circuits with Post-Silicon Clock Tuning Elements cs.AR · 2017 · author #2
  11. ILP-based Alleviation of Dense Meander Segments with Prioritized Shifting and Progressive Fixing in PCB Routing cs.AR · 2017 · author #4
  12. Post-Route Alleviation of Dense Meander Segments in High-Performance Printed Circuit Boards cs.AR · 2017 · author #4
  13. Post-Route Refinement for High-Frequency PCBs Considering Meander Segment Alleviation cs.AR · 2017 · author #4
  14. On Timing Model Extraction and Hierarchical Statistical Timing Analysis cs.AR · 2017 · author #4
  15. Statistical Timing Analysis for Latch-Controlled Circuits with Reduced Iterations and Graph Transformations cs.OH · 2017 · author #3
  16. Fast Statistical Timing Analysis for Circuits with Post-Silicon Tunable Clock Buffers cs.AR · 2017 · author #3
  17. Timing Model Extraction for Sequential Circuits Considering Process Variations cs.AR · 2017 · author #3
  18. On Hierarchical Statistical Static Timing Analysis cs.AR · 2017 · author #5
  19. Static Timing Model Extraction for Combinational Circuits cs.AR · 2017 · author #5
  20. Emulated ASIC Power and Temperature Monitor System for FPGA Prototyping of an Invasive MPSoC Computing Architecture cs.AR · 2014 · author #4

Mentions

  • 1405.2909 #4 · backfill · confidence 0.70 Ulf Schlichtmann

Frequent Coauthors