M.B Srinivas

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Papers (6)

1. Reduced Area Low Power High Throughput BCD Adders for IEEE 754r Format cs.AR · 2006 · author #3
2. VLSI Implementation of RSA Encryption System Using Ancient Indian Vedic Mathematics cs.AR · 2006 · author #2
3. Novel Reversible Multiplier Architecture Using Reversible TSG Gate cs.AR · 2006 · author #2
4. An Extension to DNA Based Fredkin Gate Circuits: Design of Reversible Sequential Circuits using Fredkin Gates cs.AR · 2006 · author #2
5. A New Reversible TSG Gate and Its Application For Designing Efficient Adder Circuits cs.AR · 2006 · author #2
6. Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format cs.AR · 2006 · author #3

Mentions

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Frequent Coauthors

• Himanshu Thapliyal 6 shared papers
• Hamid R. Arabnia 1 shared papers
• Saurabh Kotiyal 1 shared papers