Naveen Kr. Malik
Identifiers
- name variant Naveen Kr. Malik 0.60 · backfill
Papers (3)
- DSTN (Distributed Sleep Transistor Network) for Low Power Programmable Logic array Design cs.OH · 2012 · author #3
- A Cost- Effective Design of Reversible Programmable Logic Array cs.OH · 2012 · author #2
- Reversible Programmable Logic Array (RPLA) using Feynman & MUX Gates for Low Power Industrial Applications cs.AR · 2012 · author #2
Mentions
Frequent Coauthors
- Pradeep Singla 3 shared papers
- Kamya Dhingra 1 shared papers