Deja Vu packing memoizes recurring FPGA packing pattern legality checks via a signature tree, delivering average speedups of 3.7x-6.9x in packing and 1.6x-5.3x in full VPR runtime while preserving quality of results.
Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect
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D\'ej\`a Vu Packing: Optimizing FPGA Logic Clustering Runtime via Pattern Memoization
Deja Vu packing memoizes recurring FPGA packing pattern legality checks via a signature tree, delivering average speedups of 3.7x-6.9x in packing and 1.6x-5.3x in full VPR runtime while preserving quality of results.