An FPGA-based neural-network decoder achieves 550 ns deterministic closed-loop latency for real-time distance-3 surface code error correction on a superconducting processor, matching offline decoding performance.
N.et al.Ultra Low-latency, Low-area Inference Accelerators using Heterogeneous Deep Quantization with QKeras and hls4ml (2020)
3 Pith papers cite this work. Polarity classification is still indexing.
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UNVERDICTED 3representative citing papers
Neural networks integrated into silicon sensor front-end electronics can regress charged-particle hit positions and angles with calibrated uncertainties from single-layer data while satisfying hardware constraints on precision, latency, and area.
APEIRON is a distributed heterogeneous processing framework for multi-FPGA TDAQ systems in HEP that spans low-level drivers to HLS-based dataflow programming, demonstrated via a particle identification application for the NA62 experiment.
citing papers explorer
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Real-time Surface-Code Error Correction Using an FPGA-based Neural-Network Decoder
An FPGA-based neural-network decoder achieves 550 ns deterministic closed-loop latency for real-time distance-3 surface code error correction on a superconducting processor, matching offline decoding performance.
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On-chip probabilistic inference for charged-particle tracking at the sensor edge
Neural networks integrated into silicon sensor front-end electronics can regress charged-particle hit positions and angles with calibrated uncertainties from single-layer data while satisfying hardware constraints on precision, latency, and area.
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APEIRON: composing smart TDAQ systems for high energy physics experiments
APEIRON is a distributed heterogeneous processing framework for multi-FPGA TDAQ systems in HEP that spans low-level drivers to HLS-based dataflow programming, demonstrated via a particle identification application for the NA62 experiment.