Routing-aware DeepR, which enforces per-hop connection sparsity targets, yields mappable spiking networks that match an L1 baseline's accuracy with about 10x less simulated routing memory on the Mosaic architecture.
A scalable multicore architecture with heterogeneous memory structures for dynamic neuromorphic asynchronous processors (dynaps)
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Hardware architecture and routing-aware training for optimal memory usage: a case study
Routing-aware DeepR, which enforces per-hop connection sparsity targets, yields mappable spiking networks that match an L1 baseline's accuracy with about 10x less simulated routing memory on the Mosaic architecture.