A simulation-based framework using compiler-inserted probes, a two-stage sketch, and a PageRank-style ranking detects on-chip fail-slow cores/links at ~86.8% accuracy with ~116x trace compression.
2025.Architectures for Scientific Computing
1 Pith paper cite this work. Polarity classification is still indexing.
1
Pith paper citing it
fields
cs.AR 1years
2025 1verdicts
CONDITIONAL 1representative citing papers
citing papers explorer
-
SLOTH: Lightweight Detection and Localization of On-Chip Fail-Slow Failures for DNN Accelerators
A simulation-based framework using compiler-inserted probes, a two-stage sketch, and a PageRank-style ranking detects on-chip fail-slow cores/links at ~86.8% accuracy with ~116x trace compression.