A delay-driven pre-processing stage redistributes complemented edges in AIGs via self-dual transformations, yielding up to 3.86% delay improvement on EPFL benchmarks like sqrt.
Sasao,Switching Theory for Logic Synthesis
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Inverter Redistribution through Self-Dual and Self-Anti-Dual Function Transformation
A delay-driven pre-processing stage redistributes complemented edges in AIGs via self-dual transformations, yielding up to 3.86% delay improvement on EPFL benchmarks like sqrt.