Position graph abstraction plus SHAPER/SHAW heuristics enable shuttling-aware compilation on trapped-ion machines, succeeding on extreme cases where baselines fail and yielding 1.45x average (up to 4x) speedups.
Shuttling for scalable trapped-ion quantum computers
3 Pith papers cite this work. Polarity classification is still indexing.
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UNVERDICTED 3representative citing papers
A new compiler for surface codes on QCCD trapped-ion hardware shows that 2-ion traps outperform larger traps in logical clock speed and hardware efficiency, beating prior compilers by 3.8X on average.
Constructions for universal quantum computation in the [[n,n-2,2]] error-detecting code detect single-gate errors at computation end, providing weak fault tolerance with reduced overhead versus full error correction.
citing papers explorer
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Efficient Compilation for Shuttling Trapped-Ion Machines via the Position Graph Architectural Abstraction
Position graph abstraction plus SHAPER/SHAW heuristics enable shuttling-aware compilation on trapped-ion machines, succeeding on extreme cases where baselines fail and yielding 1.45x average (up to 4x) speedups.
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Architecting Scalable Trapped Ion Quantum Computers using Surface Codes
A new compiler for surface codes on QCCD trapped-ion hardware shows that 2-ion traps outperform larger traps in logical clock speed and hardware efficiency, beating prior compilers by 3.8X on average.
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Weakly Fault-Tolerant Computation in a Quantum Error-Detecting Code
Constructions for universal quantum computation in the [[n,n-2,2]] error-detecting code detect single-gate errors at computation end, providing weak fault tolerance with reduced overhead versus full error correction.