A fine-tuned LLaVA model, trained on synthetic timing-diagram Q&A pairs generated from Verilog simulations, answers design and verification questions about timing diagrams.
Verilogeval: Evaluating large language models for verilog code generation,
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TD-Interpreter: Enhancing the Understanding of Timing Diagrams with Visual-Language Learning
A fine-tuned LLaVA model, trained on synthetic timing-diagram Q&A pairs generated from Verilog simulations, answers design and verification questions about timing diagrams.