A single-timestep SNN inference accelerator on FPGA, co-designed with TET-based temporal pruning, reports competitive accuracy with lower latency and energy than two-timestep implementations.
Seenn: Towards temporal spiking early exit neural networks,
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STI-SNN: A 0.14 GOPS/W/PE Single-Timestep Inference FPGA-based SNN Accelerator with Algorithm and Hardware Co-Design
A single-timestep SNN inference accelerator on FPGA, co-designed with TET-based temporal pruning, reports competitive accuracy with lower latency and energy than two-timestep implementations.