A RISC-V design adds FSM-driven convolution and dot-product accelerators, claiming a 3.37x speedup, but provides no implementation or measurements.
The RISC-V Instruction Set Manual, Volume I: User-Level ISA,
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Design and Implementation of a RISC-V SoC with Custom DSP Accelerators for Edge Computing
A RISC-V design adds FSM-driven convolution and dot-product accelerators, claiming a 3.37x speedup, but provides no implementation or measurements.