C2C-Explorer combines an LLM-workload-driven AXI traffic generator, a hybrid cycle/event chip-to-chip simulator validated to 2.46-8.23% timing error on FPGA hardware, and Bayesian optimization to search interconnect configurations.
Architecture, Chip, and Package Co-design Flow for 2.5D IC Design Enabling Heterogeneous IP Reuse
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C2C-Explorer: An Exploration Framework for Chip-to-Chip Interconnect Architectures in LLM Cloud Computing Systems
C2C-Explorer combines an LLM-workload-driven AXI traffic generator, a hybrid cycle/event chip-to-chip simulator validated to 2.46-8.23% timing error on FPGA hardware, and Bayesian optimization to search interconnect configurations.