An NDA-safe scrubbed boundary lets cloud LLMs optimize analog circuits in real Cadence flows; multi-model PVT benchmarks show successful closure on LC-VCO (7/11) and two-stage op-amp (4/11) tasks.
AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis
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abstract
Recent advances in machine learning (ML) for automating analog circuit synthesis have been significant, yet challenges remain. A critical gap is the lack of a standardized evaluation framework, compounded by various process design kits (PDKs), simulation tools, and a limited variety of circuit topologies. These factors hinder direct comparisons and the validation of algorithms. To address these shortcomings, we introduced AnalogGym, an open-source testing suite designed to provide fair and comprehensive evaluations. AnalogGym includes 30 circuit topologies in five categories: sensing front ends, voltage references, low dropout regulators, amplifiers, and phase-locked loops. It supports several technology nodes for academic and commercial applications and is compatible with commercial simulators such as Cadence Spectre, Synopsys HSPICE, and the open-source simulator Ngspice. AnalogGym standardizes the assessment of ML algorithms in analog circuit synthesis and promotes reproducibility with its open datasets and detailed benchmark specifications. AnalogGym's user-friendly design allows researchers to easily adapt it for robust, transparent comparisons of state-of-the-art methods, while also exposing them to real-world industrial design challenges, enhancing the practical relevance of their work. Additionally, we have conducted a comprehensive comparison study of various analog sizing methods on AnalogGym, highlighting the capabilities and advantages of different approaches. AnalogGym is available in the GitHub repository https://github.com/CODA-Team/AnalogGym. The documentation is also available at http://coda-team.github.io/AnalogGym/.
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cs.AR 1years
2026 1verdicts
CONDITIONAL 1representative citing papers
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SABLE: An NDA-Safe Closed-Loop LLM Framework for Analog Circuit Optimization in Industrial EDA Flows
An NDA-safe scrubbed boundary lets cloud LLMs optimize analog circuits in real Cadence flows; multi-model PVT benchmarks show successful closure on LC-VCO (7/11) and two-stage op-amp (4/11) tasks.