SVA Generator improves semantic correctness of LLM-generated SystemVerilog Assertions by 22.7 percentage points on average for deeper properties using AST-grounded constraint injection and depth-stratified formal equivalence checking.
A survey on assertion- based hardware verification
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VeriCWEty applies embedding-based analysis to detect CWEs in Verilog with 89% precision on examples like CWE-1244/1245 and 96% accuracy at line level.
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Automated SVA Generation with LLMs
SVA Generator improves semantic correctness of LLM-generated SystemVerilog Assertions by 22.7 percentage points on average for deeper properties using AST-grounded constraint injection and depth-stratified formal equivalence checking.
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VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilog
VeriCWEty applies embedding-based analysis to detect CWEs in Verilog with 89% precision on examples like CWE-1244/1245 and 96% accuracy at line level.