Behavioral simulation shows column-drain readout reaches nearly 100% efficiency for cycles under 100 ns at hit rates up to 322.5 MHz per chip, with buffer and memory assessments for BXID-sharing format.
Design and first results of coffee3: A 55nm hvcmos pixel sensor prototype for high-energy physics applications
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Behavioral-Level Simulation of Digital Readout for COFFEE at LHCb Upstream Pixel Tracker
Behavioral simulation shows column-drain readout reaches nearly 100% efficiency for cycles under 100 ns at hit rates up to 322.5 MHz per chip, with buffer and memory assessments for BXID-sharing format.