An automatic RTL compiler generates a Stratix 10 FPGA accelerator that performs forward pass, backward pass, and weight update for CIFAR-10 CNNs in 16-bit fixed point, reporting up to 479 GOPS.
An automatic RTL compiler for high-throughput FPGA implementation of diverse deep convolutional neural networks,
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Automatic Compiler Based FPGA Accelerator for CNN Training
An automatic RTL compiler generates a Stratix 10 FPGA accelerator that performs forward pass, backward pass, and weight update for CIFAR-10 CNNs in 16-bit fixed point, reporting up to 479 GOPS.