Identification of a memory control timing issue in ABCStar ASIC and mitigation by increasing core voltage to 1.25 V and clock duty cycle to restore production yields above 80%.
Jensen, et al.,Monte Carlo Simulation of Semiconductor Devices, Computer Physics Communications, 67, pp
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Identification and mitigation of memory block timing issue in ITk ABCStar during ASIC production
Identification of a memory control timing issue in ABCStar ASIC and mitigation by increasing core voltage to 1.25 V and clock duty cycle to restore production yields above 80%.