The EPAC chip integrates three RISC-V tiles connected by a CHI network-on-chip and has been successfully taped out and validated in GF22FDX technology as part of the European Processor Initiative.
Proceedings of the SC '23 Workshops of the International Conference on High Performance Computing, Network, Storage, and Analysis , pages =
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EPAC: The Last Dance
The EPAC chip integrates three RISC-V tiles connected by a CHI network-on-chip and has been successfully taped out and validated in GF22FDX technology as part of the European Processor Initiative.
- Monte Cimone v3: Where RISC-V Stands in High-Performance Computing