A write-back aware NVM emulator estimates per-process write-back cache misses and injects proportional delays, achieving 0.1% to 1.1% error on emulated write latencies.
Phasechange memory technology,
1 Pith paper cite this work. Polarity classification is still indexing.
1
Pith paper citing it
fields
cs.DC 1years
2019 1verdicts
CONDITIONAL 1representative citing papers
citing papers explorer
-
A Software-based NVM Emulator Supporting Read/Write Asymmetric Latencies
A write-back aware NVM emulator estimates per-process write-back cache misses and injects proportional delays, achieving 0.1% to 1.1% error on emulated write latencies.