A 65-nm 6T SRAM cell with minimum-size transistors (cell ratio and pull-up ratio equal to 1) is functional and offers about 25% area, 35% leakage, and 30% soft-error improvements, provided the read word-line voltage is lowered by about 10%.
Scale changes in electronics: Implications for nanostructure devices for logic and memory and beyond,
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A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors
A 65-nm 6T SRAM cell with minimum-size transistors (cell ratio and pull-up ratio equal to 1) is functional and offers about 25% area, 35% leakage, and 30% soft-error improvements, provided the read word-line voltage is lowered by about 10%.