An FPGA-based neural-network decoder achieves 550 ns deterministic closed-loop latency for real-time distance-3 surface code error correction on a superconducting processor, matching offline decoding performance.
Real-time Surface-code Error Correction Using an FPGA-based Neural-Network Decoder
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Real-time Surface-Code Error Correction Using an FPGA-based Neural-Network Decoder
An FPGA-based neural-network decoder achieves 550 ns deterministic closed-loop latency for real-time distance-3 surface code error correction on a superconducting processor, matching offline decoding performance.