Hardware-faithful verification with a HAL descriptor eliminates all 54 false 16-bit overflow alarms on 123 real IEC 61131-3 programs while preserving robustness proofs.
Springer Nature Switzerland, Milan, Italy, September 2024
3 Pith papers cite this work. Polarity classification is still indexing.
3
Pith papers citing it
fields
cs.PL 3years
2026 3representative citing papers
ESBMC-PLC+ unifies support for all major IEC 61131-3 formats (ST, LD, SCL) in a single ESBMC backend with k-induction for unbounded safety proofs and extended function block semantics.
ESBMC-GraphPLC implements a graph traversal resolver that extracts Boolean rung logic from graphical LD connection graphs and produces complete GOTO IR, enabling verification of programs that previously yielded empty representations.
citing papers explorer
-
ESBMC-Arduino: Closing the Deployment Gap for Formal Verification of Open-Hardware PLCs
Hardware-faithful verification with a HAL descriptor eliminates all 54 false 16-bit overflow alarms on 123 real IEC 61131-3 programs while preserving robustness proofs.
-
ESBMC-PLC+: A Unified IEC 61131-3 Formal Verification Framework as a PLCverif Successor
ESBMC-PLC+ unifies support for all major IEC 61131-3 formats (ST, LD, SCL) in a single ESBMC backend with k-induction for unbounded safety proofs and extended function block semantics.
-
ESBMC-GraphPLC: Formal Verification of Graphical PLCopen XML Ladder Diagram Programs Using SMT-Based Model Checking
ESBMC-GraphPLC implements a graph traversal resolver that extracts Boolean rung logic from graphical LD connection graphs and produces complete GOTO IR, enabling verification of programs that previously yielded empty representations.