Stream-HLS automatically converts affine multi-kernel C/C++ or PyTorch programs into streaming FPGA dataflow designs using a combined MINLP scheduler, with RTL-simulated geometric mean speedups up to 79.43x over prior frameworks.
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Stream-HLS: Towards Automatic Dataflow Acceleration
Stream-HLS automatically converts affine multi-kernel C/C++ or PyTorch programs into streaming FPGA dataflow designs using a combined MINLP scheduler, with RTL-simulated geometric mean speedups up to 79.43x over prior frameworks.